University College Dublin
An Coláiste Ollscoile, ́tha Cliath
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Autumn Trimester Exams, 2021 TRIMESTER EXAMINATIONS
Copyright By PowCoder代写 加微信 powcoder
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Computer Systems
Module Coordinator: Assoc Professor
Student Number
Seat Number
Time Allowed: 120 minutes
Instructions to Students:
This is an open book exam. Attempt all questions. Enter your answers into the appropriate Assignment / Test activities on csmoodle.ucd.ie
The examination is marked out of 100 in total. A MIPS Reference is provided at the end of the examination paper.
UCD © Autumn Trimester Exams, 2021 Page 1 of 6 COMP30080
MULTIPLE CHOICE QUESTIONS
All questions in this section are worth full marks for a correct answer, 0 for an incorrect answer or no answer. In total, the questions in this section are worth 40 marks.
1. Which one of the following MIPS32 directives allocates exactly 8 bytes of memory? A. .space 16
B. .byte 7,5,6,7,3,4,5,6,9 C. .word 1,2
D. .asciiz ”hello123”
2. Consider the code fragment below. Which one of the following instructions completes the process of popping the register from the stack?
A. addi $sp, $sp, 4 B. addi $sp, $sp, -4 C. addi $sp, $sp, -8 D. li $sp, 0x7ffe0000
lw $s0, 0($sp)
3. Which of the following 32-bit words is a MIPS32 load word instruction? Information on the MIPS32 instruction format is provided in the reference section at the end of the question paper.
A. 8e080000 B. ae080000 C. bd100000 D. 6e080004
4. Consider the following code fragment. If the address of the label Loop is 0x1000, what value is stored in the address field of the assembled bne instruction?
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C. 0x1000 D. -2
add $t0, $t0, +3 addi $t1,$t1,−1
$zero , Loop
5. How long does a program with the instruction profile given in the table below take to ex- ecute on a multicycle MIPS32 processor with a 1 MHz clock and the CPI values given in the table below.
Instruction Type
Arithmetic / Logical Load
Store Branch / Jump
Instruction Count CPI
1,000 4 600 5 300 4 100 3
A. 8.5 ms B. 85 ms C. 0.2 ms D. 2 ms
6. What is the execution time of a program that requires execution of 1,000 instructions on a pipelined MIPS32 processor with a 100 MHz clock and a 10% stall rate?
A. 11 μs B. 10 μs C. 9 μs D. 10 ms
7. Consider the following fragment of code. When the fragment is executed on a pipelined MIPS processor, how many stalls occur?
A. 1 B. 0 C. 2 D. 3
lw $t1 , add $t2 , sw $t2 , lw $t1 , sw $t2 ,
0($t0) $t1 , $t0 4($t0) 4($t0) 8($t0)
8. The theoretical peak MIPS on a 2-way multiple issue processor with a 10 stage pipeline and a 2 GHz clock frequency is:
A. 4,000 B. 20,000 C. 40,000 D. 2,000
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(4 marks) Page 3 of 6
9. Consider the following code fragment. What is the miss rate when the code is executed on a MIPS32 processor with a direct mapped cache using a 3 bit offset field and a 3 bit set field?
li Loop: lw lw
A. 20 percent B. 100 percent C. 0 percent D. 10 percent
10. What are the values on top of the stack after execution of the Java bytecode instruction iadd, if the stack is set-up as shown below prior to execution of the instruction?
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A. TOS=7 and NOS=7 B. TOS=7 and NOS=2 C. TOS=14 and NOS=2 D. TOS=7 and NOS=5
$t1 , 0x1008 ( $0 ) $t3 , 0x1010 ( $0 ) $t0, $t0, −1
$t0 , $zero , Loop
LONG QUESTIONS
In total, the questions in this section are worth 60 marks.
11. Write a MIPS32 assembly function in MARS simulator that will replace all lower case let- ters in a string with their upper case equivalents. All other characters should be left un- changed. The input and output strings should be terminated by a full stop. The output string should overwrite the input string in memory. For example, given the input “Comp 30080.”, the program output should be “COMP 30080.”. Sample ASCII codes are provided in the Reference section at the end of the question paper.
(40 marks)
12. (a) Identify and briefly discuss any of the features of Java Bytecode that makes it more resilient to stack overflow exploitation attacks than MIPS instruction set architecture.
(10 marks) (b) Briefly explain what loop unrolling is and how it is used to speed up program execution
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in a static multiple issue processor.
(10 marks)
REFERENCE Inst.
add rd,rs,rt sub rd,rs,rt addi rt,rs,c
lw rt,c(rs)
sw rt,c(rs) beq rs,rt,addr bne rs,rt,addr jaddr jaladdr
Table 1: MIPS32 Instruction
Codes (-=not applicable)
R R I I I I I
rs rt rd shamt funct
addr/const
– constant offset offset relative address relative address address address
3510 base 4310 base 410 reg 510 reg
dst – – dst – – dst – – reg – – reg – –
– – – – – – –
src src dst 0 3210 src src dst 0 3410
J 210 – – – – J 310 – – – –
R-format I-format J-format
funct 6bits 5bits 5bits 5bits 5bits 6bits
Table 2: MIPS32 Instruction Format
op rs rt rd shamt
op 6 bits op 6 bits
constant or address 16 bits
address 26 bits
Table 3: MIPS32 Register Codes (n/a=not applicable)
$zero $v0 – $v1 $a0 – $a3 $t0 – $t7 $s0 – $s7 $t8 – $t9 $gp $sp $fp $ra
0 2-3 4-7 8-15 16-23 24-25 28 29 30 31
Usage Preserved
Constant n/a Result values no Arguments no Temporary no
Saved yes More temporary no
Global pointer yes Stack pointer yes Frame pointer yes Return address yes
Table 4: Sample ASCII Codes (decimal)
0 48 9 57 A 65 Z 90 a 97 z 122
ASCII Code
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