WINTER TRIMESTER EXAMINATIONS ACADEMIC YEAR 2021/2022
COMP 30080 Computer Systems
Resit Exam
Assoc. Prof. P. Gladyshev*
Copyright By PowCoder代写 加微信 powcoder
Time Allowed: 2 Hours
This is an open book exam. Please email your answers to as an electronic cdocument in .DOCX or .PDF format within 2 hours of receiving| this paper.
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MULTIPLE CHOICE QUESTIONS
Answer the following questions on the multiple choice answer sheet provided.All questions in this section are worth 4 marks for a correct answer,0 for an incorrect answer and 0 for no answer. In total, the questions in this section are worth 40 marks.
1. Consider the code fragment below.Which one of the following instructions completes the process of popping (restoring) the register to the stack?
lw$s0, 0($sp)
A. addi $sp, $sp, -4 B. addi $sp, $sp, 4 C. sw $s0, 0($sp) D. jr $ra
2. Consider the following code fragmentI.f the address of the label Loop is 0x2000, what value is stored in the address field of the assembled bne instruction?
C. 0x2000 D. -16
add $t0 , $t0 , +3 addi $t1, $t1, −1
$zero , Loop
3. On a single cycle MIPS32 processor with a clock frequency of 20 MHz, how long does a program that requires execution of 2,000 instructions take to perform?
A. 1ms B. 10 ms C. 100 ms D. 0.1 ms
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4. How long does a program with the instruction profile given in the table below take to exe- cute on a multicycle MIPS32 processor with a 10 MHz clock and the CPI values given in the table below.
Instruction Type Arithmetic / Logical
Load Store Branch / Jump
Instruction Count CPI 1,000 4 500 5 200 4 200 3
A. 190 μs B. 19 μs C. 790 μs D. 47 μs
5. Consider the following fragment of code. When the fragment is executed on a pipelined MIPS processor, which one of the following statements is true?
lw$s1, 0($t1) sub $t3 , $s1 , $s3
A. The fragment contains a structural hazard
B. The fragment contains a data dependency which cannot be resolved by forward- ing
C. The fragment contains a data dependency which can be resolved by forwarding
D. The fragment does not contain a data dependency
6. Consider the following fragment of code. When the fragment is executed on a pipelined MIPS processor, how many stalls occur?
lw $t1, 0($t0) add $t2, $t1, $t0 sw $t2, 4($t0) lw $t1, 4($t2) sw $t2, 8($t1)
A. 1 B. 3 C. 2 D. 0
7. Consider the following fragment of code. How many pipeline flushes will occur if the code fragmentis executed on a pipelined MIPS processor with dynamic branch prediction? Assume that the initial prediction is that the branch is not taken.
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A. 1 B. 2 C. 3 D. 4
is 1 ns and the access time of access time?
A. 12ns B. 11 ns C. 10ns D. 9 ns
main memory is 100 ns. What is the average memory
li Loop: addi addi
$t1 , $t2 , $t2, $t1, $t1 ,
$t2, $t1 $t1, −1 $zero , Loop
8. The theoretical peak MIPS on a 4-way multiple issue processor with a 5 stage pipeline and a 2 GHz clock frequency is:
A. 2,000 B. 10,000 C. 40,000 D. 80,000
9. The memory hierarchy has only two levels: the cache and the main memoryA. program performs 1,000 load instructions. The cache has a 90% hit rate. The access time of cache
10. What are the values on top of the stack after execution of the Java bytecode instruction iadd, if the stack is set-up as shown below prior to execution of the instruction?
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A. TOS=18 and NOS=3 B. TOS=18 and NOS=18 C. TOS=18 and NOS=15 D. TOS=15 and NOS=3
LONG QUESTIONS
11. Write a MIPS32 assembly language program using MARS simulator that will obfuscate a string held in memory by replacing each Latin letter with the next letter in the alphabet. That is, all A’s will be replaced with B’s, all B’s will be replaced with C’s and so on, and finally allZ’s will be replaced with A’s.The same rule applied to lower case letters, while the rest of characters remain unmodified. The input string should be terminated by a full stop. The resultant string should be printed to the console using appropriate syscall.
For example an input string defined in the program as DataIn:.ascii ”Hello123.”
should be obfuscated and printed to console as Ifmmp 123.
(40 marks)
12. Provide an outline diagram showing the organisation of a single-cycle MIPS32
processor. Include the main components and their inter-connection. oOo
(20 marks)
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Inst. Format op rs rt
add rd,rs,rt R 0 src src subrd,rs,rt R 0 src src
Table 1: MIPS32 Instruction Codes (-=not applicable)
addi rt,rs,c
lw rt,c(rs)
sw rt,c(rs) beq rs,rt,addr bne rs,rt,addr jaddr jaladdr
R-format I-format J-format
rd shamt funct dst 0 3210 dst 0 3410
addr/const –
constant offset offset
relative address relative address address
base dst – – base dst – –
reg reg – –
– – – – – – –
Table 2: MIPS32 Instruction Format op rs rt rd shamt
I 810 I 3510 I 4310 I 410 I 510
reg reg – – J 210 – – – – J 310 – – – –
funct 6bits 5bits 5bits 5bits 5bits 6bits
op 6 bits op 6 bits
constant or address
address 26 bits
Table 3: MIPS32 Register Codes (n/a=not applicable)
Name Number $zero 0
$v0 – $v1 2-3 $a0 – $a3 4-7
$t0 – $t7 8-15 $s0 – $s7 16-23 $t8 – $t9 24-25
$gp 28 $sp 29 $fp 30 $ra 31
Usage Preserved Constant n/a
Result values no Arguments no Temporary no
Saved yes More temporary no Global pointer yes
Stack pointer yes Frame pointer yes Return address yes
Table 4: Sample ASCII Codes (decimal) Character ASCII Code
space 32 . 46 0 48 9 57 A 65 Z 90 a 97
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