Flow Chart Decisions
$t1 == $t2?
Branch Instructions
beq $t5, $t3, my_label
Short for branch if equal
If $t5 == $t3 then go to my_label
Otherwise, continues to the next instruction
Branch Instructions
bne $t1, $t7, my_label
Short for branch if not equal
If $t1 != $t7 then go to my_label
Otherwise, continues to the next instruction
Lecture Question
The instruction, bne $t7, $t7, target_label, will…
Always be taken
Never be taken
Not enough information given
Branch Delay Slot
There is a delay of one cycle before a branch takes effect
This means the instruction immediately after a branch instructions is always executed
PLP/MIPS Pipeline
What should be in a branch delay slot?
2 Choices:
Use a nop instruction
Short for no operation
Takes up one cycle doing nothing
Put an instruction that:
Doesn’t effect the branch
Expected to run regardless of the branch outcome
Branch Delay Slot
Important: Jump instructions also have a branch delay after them
Same considerations apply
The delay slot wasn’t an issue in Project 1 because the jump was the last instruction
Pseudo-Operations
Similar to a macro
Assembler replaces a pseudo-op with a set of one or more native instructions
Load immediate (li) is a pseudo-op made up of two separate native instructions
Takes two cycles to complete
If placed in a branch delay slot, only first half is executed
Example Situation
Assume $a0 already contains some value
If register $a0 contains a 1
Set $v0 to 2
If register $a0 contains any other value
Set $v0 to 4
Example Pseudo Code
if($a0 == 1) // if condition check
$v0 = 2; // if block
else // else condition
$v0 = 4; // else block
Solution Breakdown
If condition check
Else block
Control Flow Visualization
Expected Result
$v0 set to 4
Control Flow Visualization
Expected Result
$v0 set to 2
Demo of Code
My Code Layout Preferences
Indentation for the following:
Collection of related subroutines placed in a separate ASM file
Pseudo object oriented approach
Label Indent Example
Branch Indent Example
Multiple ASM Files
PLPTool allows additional ASM files to be included in a .plp project file
ASM can either be:
New (blank) ASM file
Imported (existing .asm file; plain text)
Multiple ASM File Demo
For Loop Demo
PLPTool and Project 2 Tips
Keep I/O Panels Open
If you click save while in simulation mode with the I/O windows you are using open, those settings will be saved
Next time you open your project and toggle on simulation mode they will all appear
Common Errors:
Memory Accesses
Lecture Question
What instruction would most likely cause the following error message in PLPTool:
[ERROR] #262 MemModule: read(0x00000001): Requested address is unaligned.
What does the error mean?
[ERROR] #262 MemModule: read(0x00000001): Requested address is unaligned.
“MemModule: read…”
This means a memory location was being read
“read(0x00000001)”
Address pointed to was 1 (== 0x1)
What does the error mean?
Example instruction that would produce this error:
$t0 has the value 1
Instruction:
lw $t1, 0($t0)
What Is the “Word” in LW and SW
A specific amount of data as defined by the instruction set architecture (ISA)
Often same as the memory address size
i.e. 32-bit processors use 32 bits to represent memory addresses and have a 32 bit word
An address is a single word
What Is the “Word” in LW and SW
The load word (lw) and store word (sw) instructions move a single word (32 bits in PLP) between memory and a register
Each valid memory address maps to 1 word (32 bits or 4 bytes) of data
Memory Access and Alignment
Memory is byte addressable
Each address represents a byte of data in memory
Memory is word aligned
Valid addresses are multiples of 4
PLPTool generates an error when an unaligned memory address is accessed
Lecture Question
Which of the following addresses isn’t word aligned?
0x10000000
0x10000004
0x10000008
0x1000000b
0x1000000c
Common Error:
Unhandled Branch Delay Slot
Branch Delay Slot
Branch Instruction
Branch Delay Slot
Branch Instructions
Branch Delay Slot For Line 7
Branch Delay Slot For 6 Line
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