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Instructions: Language of the Computer

The University of Adelaide, School of Computer Science

The University of Adelaide, School of Computer Science
Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Instruction Set
The repertoire of instructions of a computer
Different computers have different instruction sets
But with many aspects in common
Early computers had very simple instruction sets
Simplified implementation
Many modern computers also have simple instruction sets

§2.1 Introduction

Chapter 2 — Instructions: Language of the Computer — *
The University of Adelaide, School of Computer Science
The University of Adelaide, School of Computer Science
Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
The RISC-V Instruction Set
Used as the example throughout the book
Developed at UC Berkeley as open ISA
Now managed by the RISC-V Foundation (riscv.org)
Typical of many modern ISAs
See RISC-V Reference Data tear-out card
Similar ISAs have a large share of embedded core market
Applications in consumer electronics, network/storage equipment, cameras, printers, …

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Arithmetic Operations
Add and subtract, three operands
Two sources and one destination

add a, b, c // a gets b + c
All arithmetic operations have this form
Design Principle 1: Simplicity favours regularity
Regularity makes implementation simpler
Simplicity enables higher performance at lower cost

§2.2 Operations of the Computer Hardware

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Arithmetic Example

f = (g + h) – (i + j);
Compiled RISC-V code:

add t0, g, h // temp t0 = g + h
add t1, i, j // temp t1 = i + j
add f, t0, t1 // f = t0 – t1

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Register Operands
Arithmetic instructions use register

RISC-V has a 32 × 64-bit register file
Use for frequently accessed data
64-bit data is called a “doubleword”
32 x 64-bit general purpose registers x0 to x30
32-bit data is called a “word”

Design Principle 2: Smaller is faster
c.f. main memory: millions of locations

§2.3 Operands of the Computer Hardware

Chapter 2 — Instructions: Language of the Computer

RISC-V Registers
x0: the constant value 0
x1: return address
x2: stack pointer
x3: global pointer
x4: thread pointer
x5 – x7, x28 – x31: temporaries
x8: frame pointer
x9, x18 – x27: saved registers
x10 – x11: function arguments/results
x12 – x17: function arguments

Chapter 2 — Instructions: Language of the Computer — *

Chapter 2 — Instructions: Language of the Computer — *
Register Operand Example

f = (g + h) – (i + j);
f, …, j in x19, x20, …, x23

Compiled RISC-V code:

add x5, x20, x21
add x6, x22, x23
sub x19, x5, x6

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Memory Operands
Main memory used for composite data
Arrays, structures, dynamic data
To apply arithmetic operations
Load values from memory into registers
Store result from register to memory
Memory is byte addressed
Each address identifies an 8-bit byte
RISC-V is Little Endian
Least-significant byte at least address of a word
c.f. Big Endian: most-significant byte at least address
RISC-V does not require words to be aligned in memory
Unlike some other ISAs

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Memory Operand Example

A[12] = h + A[8];
h in x21, base address of A in x22
Compiled RISC-V code:
Index 8 requires offset of 64
8 bytes per doubleword

ld x9, 64(x22)
add x9, x21, x9
sd x9, 96(x22)

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Registers vs. Memory
Registers are faster to access than memory
Operating on memory data requires loads and stores
More instructions to be executed
Compiler must use registers for variables as much as possible
Only spill to memory for less frequently used variables
Register optimization is important!

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Immediate Operands
Constant data specified in an instruction

addi x22, x22, 4

Make the common case fast
Small constants are common
Immediate operand avoids a load instruction

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Unsigned Binary Integers
Given an n-bit number

Range: 0 to +2n – 1
0000 0000 … 0000 10112
= 0 + … + 1×23 + 0×22 +1×21 +1×20
= 0 + … + 8 + 0 + 2 + 1 = 1110
Using 64 bits: 0 to +18,446,774,073,709,551,615

§2.4 Signed and Unsigned Numbers

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
2s-Complement Signed Integers
Given an n-bit number

Range: –2n – 1 to +2n – 1 – 1
1111 1111 … 1111 11002
= –1×231 + 1×230 + … + 1×22 +0×21 +0×20
= –2,147,483,648 + 2,147,483,644 = –410
Using 64 bits: −9,223,372,036,854,775,808
to 9,223,372,036,854,775,807

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
2s-Complement Signed Integers
Bit 63 is sign bit
1 for negative numbers
0 for non-negative numbers
–(–2n – 1) can’t be represented
Non-negative numbers have the same unsigned and 2s-complement representation
Some specific numbers
0: 0000 0000 … 0000
–1: 1111 1111 … 1111
Most-negative: 1000 0000 … 0000
Most-positive: 0111 1111 … 1111

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Signed Negation
Complement and add 1
Complement means 1 → 0, 0 → 1

Example: negate +2
+2 = 0000 0000 … 0010two
–2 = 1111 1111 … 1101two + 1
= 1111 1111 … 1110two

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Sign Extension
Representing a number using more bits
Preserve the numeric value
Replicate the sign bit to the left
c.f. unsigned values: extend with 0s
Examples: 8-bit to 16-bit
+2: 0000 0010 => 0000 0000 0000 0010
–2: 1111 1110 => 1111 1111 1111 1110

In RISC-V instruction set
lb: sign-extend loaded byte
lbu: zero-extend loaded byte

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Representing Instructions
Instructions are encoded in binary
Called machine code

RISC-V instructions
Encoded as 32-bit instruction words
Small number of formats encoding operation code (opcode), register numbers, …
Regularity!

§2.5 Representing Instructions in the Computer

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Hexadecimal
Compact representation of bit strings
4 bits per hex digit

Example: eca8 6420
1110 1100 1010 1000 0110 0100 0010 0000

0 0000 4 0100 8 1000 c 1100
1 0001 5 0101 9 1001 d 1101
2 0010 6 0110 a 1010 e 1110
3 0011 7 0111 b 1011 f 1111

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
RISC-V R-format Instructions
Instruction fields
opcode: operation code
rd: destination register number
funct3: 3-bit function code (additional opcode)
rs1: the first source register number
rs2: the second source register number
funct7: 7-bit function code (additional opcode)

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
R-format Example
add x9,x20,x21
0000 0001 0101 1010 0000 0100 1011 0011two =
015A04B316

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
RISC-V I-format Instructions
Immediate arithmetic and load instructions
rs1: source or base address register number
immediate: constant operand, or offset added to base address
2s-complement, sign extended
Design Principle 3: Good design demands good compromises
Different formats complicate decoding, but allow 32-bit instructions uniformly
Keep formats as similar as possible

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
RISC-V S-format Instructions
Different immediate format for store instructions
rs1: base address register number
rs2: source operand register number
immediate: offset added to base address
Split so that rs1 and rs2 fields always in the same place

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Stored Program Computers
Instructions represented in binary, just like data
Instructions and data stored in memory
Programs can operate on programs
e.g., compilers, linkers, …
Binary compatibility allows compiled programs to work on different computers
Standardized ISAs

The BIG Picture

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Logical Operations
Instructions for bitwise manipulation

Useful for extracting and inserting groups of bits in a word

§2.6 Logical Operations
Operation C Java RISC-V
Shift left << << slli Shift right >> >>> srli
Bit-by-bit AND & & and, andi
Bit-by-bit OR | | or, ori
Bit-by-bit XOR ^ ^ xor, xori
Bit-by-bit NOT ~ ~

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Shift Operations
immed: how many positions to shift
Shift left logical
Shift left and fill with 0 bits
slli by i bits multiplies by 2i
Shift right logical
Shift right and fill with 0 bits
srli by i bits divides by 2i (unsigned only)

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *

AND Operations
Useful to mask bits in a word
Select some bits, clear others to 0

and x9,x10,x11
00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000
00000000 00000000 00000000 00000000 00000000 00000000 00001100 00000000

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *

OR Operations
Useful to include bits in a word
Set some bits to 1, leave others unchanged

or x9,x10,x11
00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000
00000000 00000000 00000000 00000000 00000000 00000000 00111101 11000000

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *

XOR Operations
Differencing operation
Set some bits to 1, leave others unchanged

xor x9,x10,x12 // NOT operation
00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000
11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111
11111111 11111111 11111111 11111111 11111111 11111111 11110010 00111111

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Conditional Operations
Branch to a labeled instruction if a condition is true
Otherwise, continue sequentially

beq rs1, rs2, L1
if (rs1 == rs2) branch to instruction labeled L1

bne rs1, rs2, L1
if (rs1 != rs2) branch to instruction labeled L1

§2.7 Instructions for Making Decisions

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Compiling If Statements

if (i==j) f = g+h;
else f = g-h;
f, g, … in x19, x20, …
Compiled RISC-V code:

bne x22, x23, Else
add x19, x20, x21
beq x0,x0,Exit // unconditional
Else: sub x19, x20, x21
Assembler calculates addresses

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Compiling Loop Statements

while (save[i] == k) i += 1;
i in x22, k in x24, address of save in x25
Compiled RISC-V code:

Loop: slli x10, x22, 3
add x10, x10, x25
ld x9, 0(x10)
bne x9, x24, Exit
addi x22, x22, 1
beq x0, x0, Loop

Chapter 2 — Instructions: Language of the Computer

Chapter 2 — Instructions: Language of the Computer — *
Basic Blocks
A basic block is a sequence of instructions with
No embedded branches (except at end)
No branch targets (except at beginning)

A compiler identifies basic blocks for optimization
An advanced processor can accelerate execution of basic blocks

Chapter 2 — Instructions: Language of the Computer — *
The University of Adelaide, School of Computer Sci

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