Microprocessors & Interfacing
Serial Input/Output (II)
Lecturer :
COMP9032, Week9 1
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• USART in AVR
Lecture Overview
COMP9032, Week9 2
• USART: Universal Synchronous Asynchronous Receiver and Transmitter
• Four USART units
– Units 0-3
• Each unit can be configured for synchronous or asynchronous serial communication
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AVR USART (cont.)
• Support many frames
• Have transmission error detection function
– Odd or even parity error – Framing error
– Overrun error
• Three interrupts on
– TX (Transmit) Complete – RX (Receive) Complete – TX Data Register Empty
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USART Block Diagram*
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AVR USART Structure
• The USART has three components: clock generator, transmitter and receiver
• Clockgenerator
– consists of synchronization logic for external clock input and the baud rate generator
• Baud rate: the maximum number of bits that can be transferred per second
• Transmitter
– consists of a single write buffer, a serial Shift Register, Parity Generator and Control Logic for handling different frames.
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AVR USART Structure (cont.)
• Receiver
– The receiver is the most complex part of the USART module due to its clock and data recovery operations.
– In addition to the recovery units, the receiver includes Parity Checker, Control Logic, Shift Register and Receive Buffer (UDR).
– The Receiver supports the same frame formats as the Transmitter, and can detect Framing Error, Data Overrun and Parity Error.
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Frame Format
• Up to 30 different formats available in the USART
– combinations of
• 1 start bit (St)
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit (P) • 1 or 2 stop bits (Sp)
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Parity Bit
• Used to check whether the received data is different from the sending data
– A very simple way
• Two forms of the parity bit
– Even parity
P =dd dd0 even n n−1 1 0
– Odd parity
P =dd dd1 odd n n−1 1 0
– Where di in the above two formulas is a data bit, n is the number of data bits.
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Control State Registers
• Three control state registers are used in the USART operation:
• for storing the status flags of USART
• for controlling transmission speed and use of multiple processors
• for enabling interrupts, transmission operations • for setting frame format
• for bit extension
• For operation configuration
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• USART Control and Status Register A
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UCSRA Bit Description
• Bit 7 – RXC: USART Receive Complete
– Set when the receive buffer is not empty
– The RXC flag can be used to generate a Receive Complete interrupt
• Bit 6 – TXC: USART Transmit Complete
– Set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data present in the transmit buffer
– TXC can generate a Transmit Complete interrupt
– TXC is automatically cleared when a transmit complete interrupt is executed.
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UCSRA Bit Description (cont.)
• Bit 5 – UDRE: USART Data Register Empty
– Set when the transmit buffer (UDR) is empty
– Can be used to generate a Data Register Empty interrupt
• Bit 4 – FE: Frame Error
– Set when the character in the receive buffer was transferred in a wrong frame.
• Bit 3 – DOR: Data OverRun
– Set when a Data OverRun condition is detected.
– A Data OverRun occurs when the receive buffer is full and a new start bit is detected.
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UCSRA Bit Description (cont.)
• Bit 2 – UPE: USART Parity Error
– Set when the character in the receive buffer had a Parity Error when received and the Parity Checking was enabled
• Bit 1 – U2X: Double the USART Transmission Speed
– Set for doubling the transfer rate for asynchronous communication
• Bit 0 – MPCM: Multi-processor Communication Mode
– If set, all the incoming frames received by the USART Receiver that do not contain address information will be ignored.
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• USART Control and Status Register B
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UCSRB Bit Description
• Bit 7 – RXCIE: RX Complete Interrupt Enable
– Set to enable interrupt on the RXC flag
• Bit 6 – TXCIE: TX Complete Interrupt Enable
– Set to enable interrupt on the TXC flag
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
– Set to enable interrupt on the UDRE flag.
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UCSRB Bit Description (cont.)
• Bit 4 – RXEN: Receiver Enable
– Set to enable the USART receiver.
– The Receiver will override normal port operation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FE, DOR and UPE flags.
• Bit 3 – TXEN: Transmitter Enable
– Set to enable the USART Transmitter
– The Transmitter will override normal port operations for the TxD pin when enabled. Disabling the Transmitter will not become effective until transmissions are complete.
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UCSRB Bit Description (cont.)
• Bit 2 – UCSZ2: Character Size
– The bit combined with the UCSZ1:0 bits in UCSRC sets the number of data bits in a frame.
• Bit 1 – RXB8: Receive Data Bit 8
– The ninth data bit of the received character when operating with serial frames with 9-bit data. Must be read before reading the low bits from UDR
• Bit 0 – TXB8: Transmit Data Bit 8
– The ninth data bit in the character to be transmitted when operating with serial frames with 9-bit data. Must be written before writing the low bits to UDR
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• USART Control and Status Register C
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UCSRC Bit Description
• Bit 6 – UMSEL: USART Mode Select
– 0: Asynchronous Operation – 1: Synchronous Operation
• Bit 5:4 – UPM1:0: Parity Mode
– Set to enable Parity bit operation
UPM1 UPM0 Parity Mode
Enabled, Even Parity Enabled, Odd Parity
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UCSRC Bit Description (cont.)
• Bit 3 – USBS: Stop Bit Select
– 0: 1-bit – 1: 2-bit
• Bit 2:1 – UCSZ1:0: Character Size
– Together with UCSZ2 to determine the number of bits for a character
UCSZ2 UCSZ1 UCSZ0 Character Size
0 0 0 0 0 1
0 Reserved 1 Reserved 0 Reserved
1 1 1 9-bit
COMP9032, Week9
UCSRC Bit Description (cont.)
• Bit0–UCPOL:ClockPolarity
UCPOL Sampled
Transmitted Data Changed (Output of TxD Pin)
Rising XCK Edge Failing XCK Edge
Received Data
(Input on RxD Pin)
Failing XCK Edge Rising XCK Edge
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USART Initialization
• Initialization process consists of
– Setting the baud rate,
– Setting the frame format and
– Enabling the Transmitter and/or the Receiver
• For interrupt driven USART operations, the Global Interrupt Flag should be cleared when doing the initialization
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Sample Code
• Initialize USART 1
.macro: USART_Init:
; Set baud rate, which is stored in r17:r16
sts UBRR1H, r17 sts UBRR1L, r16
; Enable receiver and transmitter
ldi r16, (1<