CSC342/343
Laboratory Exercise: DESIGN ARITHMETIC LOGIC UNIT Instructor :Professor Isidor Gertner
Submission Date By April 10, 2021 BY 10:00 PM
What to Submit:
Copyright By PowCoder代写 加微信 powcoder
• Comprehensive REPORT
• Archived file for verification(QAR) + README on how to verify your design.
• Complete VHDL code in the report
• Waveforms must be included in the report and explained.
Please hand write and sign statements affirming that you will not cheat here and in your submission:
“I will neither give nor receive unauthorized assistance on this LAB. I will use only one computing device to perform this LAB” .
1. Implement in VHDL MIPS Instructions shown in the table.
2. Verify correctness in ModelSim Simulation using waveforms
for several select cases
3. Compare the execution of instructions you have designed
with corresponding MIPS instructions in MARS environment.
What to do:
You will need to use 3-ported RAM (2 Reads,
1 write) as a REGISTER FILE, and access
• Three 32-bit registers RT,RS,RD,from REGISTER FILE! Create IR- instruction register where you
store each instruction you are executing
• In IR you access registers RT,RS,RD, and/or 16-bit IMM16 as specified by instruction.
Create DATA MEMORY: 1-Ported RAM you have
• 32-bitMemoryAddressRegister(MAR)toaccess(1-portedRAM LPM) in DATA MEMORY
• 32-Bit Memory Data Register (MDR) to access DATA MEMORY 1
CSC342/343
Laboratory Exercise: DESIGN ARITHMETIC LOGIC UNIT Instructor :Professor Isidor Gertner
Submission Date By April 10, 2021 BY 10:00 PM
Second, Design arithmetic logic unit comprised of ADD/SUB and
Bitwise operations, with flags.
Third, Run simulations and verification s for all instructions
and compare with MIPS instructions in MARS.
The instructions are taken from “green pages”
Arithmetic
Add Immediate
Add Imm. Unsigned
Add Unsigned
Subtract Unsigned
Bitwise Logical
And Immediate
Or Immediate
Shift Left
LSohgiifctalRight
SLhoigfitcRailghtArith sra R
Memory access
Store Word sw I Load Word lw I
Components you need:
Format Operation
add R addi I
R[rd] = R[rs] + R[rt] R[rt] = R[rs] + SignExtImm R[rt] = R[rs] + SignExtImm R[rd] = R[rs] + R[rt R[rd] = R[rs] – R[rt] R[rd] = R[rs] – R[rt]
R[rd] = R[rs] & R[rt]
R[rt] = R[rs] & ZeroExtImm
R[rd] = ~ (R[rs] |R[rt])
R[rt] = R[rs] | ZeroExtImm
R[rd] = R[rt] << shamt
R[rd] = R[rt] >> shamt
R[rd] = R[rt] >>> shamt
M[R[rs]+SignExtImm] = R[rt] R[rt] = M[R[rs]+SignExtImm]
addiu I addu R R sub R subu R
and R andi I nor R
ori I sll R srl R
Register File, Data Memory you have designed.
You need to access 32-bit registers: RS,RT,RD and in data memory
1 ADD/SUB unit with flags Overflow, Negative, Zero
1 Bitwise operation unit
CSC342/343
Laboratory Exercise: DESIGN ARITHMETIC LOGIC UNIT Instructor :Professor Isidor Gertner
Submission Date By April 10, 2021 BY 10:00 PM
Design R Format Instructions
DATA FLOW (DATA PATH FOR R_FORMAT INSTRUCTIONS)
Operations
1. add 2. addu 3. sub 4. subu 5. and 6. nor 7. or
R[rd] = R[rs] operation R[rt]
4-bit operation code {0000}
Operation decoder
Logical Bitwise Ops
RS 32-bit Register
RD 32-bit Register
Rt 32-bit Register
1. Use or Design add/sub including flags Z,N,O as in self- check lab you have done
2. Design Logical bitwise ops unit
3. Design operation decoder unit that will select one
operation to execute (out of 7 shown above), based on 4 –
bit operations code.
CSC342/343
Laboratory Exercise: DESIGN ARITHMETIC LOGIC UNIT Instructor :Professor Isidor Gertner
Submission Date By April 10, 2021 BY 10:00 PM
4. Verify the correctness of all instructions in simulation by comparing the results with MIPS instructions in MARS.
What to submit: Report, video, sourc code QAR VHDL code printout, Waveforms showing opcode, operands, results, and compare with corresponding MIPS instructions.
Design R Format Instructions
DATA FLOW (DATA PATH FOR R_FORMAT SHIFT INSTRUCTIONS)
Operations 1.ShiftLeftLogical SLL
R[rd] = R[rt] << shmat(shift amount)Specified in IMM field 2.ShiftRightLogical SRL
R[rd] = R[rt] >> shmat(shift amount)Specified in IMM field 3.ShiftRightArithmetic SRA
R[rd] = R[rt] >>> shmat(shift amount)Specified in IMM field
4-bit operation code {0000}
Operation decoder
Logical Bitwise Ops
IMM 16-bit Register stores Shift Amount
1. Extend the design in part Ia to include shift operations as shown above.
2. Verify the correctness of all instructions in simulation by comparing the results with MIPS instructions in MARS.
RD 32-bit Register
RT 32-bit Register
CSC342/343
Laboratory Exercise: DESIGN ARITHMETIC LOGIC UNIT Instructor :Professor Isidor Gertner
Submission Date By April 10, 2021 BY 10:00 PM
What to submit: VHDL code printout, Waveforms showing opcode,
operands, results, and compare with corresponding MIPS
instructions.
Design I Format Instructions
DATA FLOW (DATA PATH FOR I Format _Arithmetic/Logic INSTRUCTIONS)
Operations
1. addi 2. addiu 3. subu 4. andi 5. ori
R[rt] = R[rs] operation (SignExtImm or ZeroExtImm)
4-bit operation code {1,2,…7}
16-bit IMM Register
Zero Extension or Sign extension
16-bit -> 32-bit
RD 32-bit Register
Rs 32-bit Register
Extend code in Part I to include Zero Extension or Sign
Extension unit as show in the figure. The 16 to 32 bit extension
is controlled by signal if (S=1 ) the do sign extension else do
zero extension.
What to Submit:
Same as in Part I for Format I instructions.
Suggested operands:
CSC342/343
Laboratory Exercise: DESIGN ARITHMETIC LOGIC UNIT Instructor :Professor Isidor Gertner
Submission Date By April 10, 2021 BY 10:00 PM
N=32 bits using Most positive, Most negative integer as a first
operand, and integers +1, -1, +2, -2 as a second operand. You
have to demonstrate that flags OVERFLOW, ZERO, NEGATIVE are set
correctly.
DATA FLOW (DATA PATH FOR MEMORY ACCESS INSTRUCTIONS FORMAT I) Operations
Load Word lw I R[rt] = M[R[rs]+SignExtImm] MAR -Memory Address Register
MDR -Memory Data (for the purpose of lab demo initialize MDR to any 32-bit data) 1. Memory Address computation
MAR = R[rs] operation SignExtImm
2. Copy data from MDR to Rt, R[rt] <= MDR
4-bit operation code {1,2,...7}
16-bit IMM Register
Sign extension 16-bit -> 32-bit
Modify Part II to compute effective address.
What to submit:
Same as in Part II PLUS Show Content of register MAR, and RT.
Compare with MIPS LW instruction.
Abstract Memory Ports
32-bit Registe
Rs 32-bit Register
CSC342/343
Laboratory Exercise: DESIGN ARITHMETIC LOGIC UNIT Instructor :Professor Isidor Gertner
Submission Date By April 10, 2021 BY 10:00 PM
DATA FLOW (DATA PATH FOR MEMORY ACCESS INSTRUCTIONS) Operations
Store Word sw I M[R[rs]+SignExtImm] = R[rt] MAR -Memory Address Register
MDR -Memory Data Register 1. Memory Address computation
MAR = R[rs] operation SignExtImm
2. Copy data from Rt to MDR, R[rt] <= MDR
4-bit operation code {1,2,...7}
16-bit IMM Register
Same as in part III.
What Submit:
Sign extension 16-bit -> 32-bit
Abstract Memory Ports
Rs 32-bit Register
RT – 32-Bit Register
Modify Part II to compute effective address.
What to submit:
Same as in Part III PLUS Show Content of register MAR,MDR and
RT. Compare with MIPS SW instruction.
CSC342/343
Laboratory Exercise: DESIGN ARITHMETIC LOGIC UNIT Instructor :Professor Isidor Gertner
Submission Date By April 10, 2021 BY 10:00 PM
程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com