程序代写 SOF108 COMPUTER ARCHITECTURE TUTORIAL 5: Instruction Set Architecture – I

SOF108 COMPUTER ARCHITECTURE TUTORIAL 5: Instruction Set Architecture – I
1. Compare zero, one, two, and three-address machines by writing instructions to compute the following.
i) X = (A + B) ∗ (C + D)
The instructions available for use are as follows:

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0 Address Stack
PUSH X Push the word at address X to the top of the Stack POP XPop the word from the top of stack to address X ADD  Add the top two elements in the stack
MUL  Multiply the top two elements in the stack
1 Address Accumulator
 AC←AC+M[X]
 AC←AC*M[X]
 R1←R1+M[X]
MUL R1, R2
 R1 ← R1∗R2
MUL R1, R2
R1 ← R1∗R2
ADD R1, X, Y
 R1←M[X]+M[Y]
MUL X, R1, R2
 M[X]←R1∗R2
* TOS = Top of Stack

2. Write the instructions for computing Y = (A-B) / (C + (D * E)) based on a stack architecture. You may refer to the table in question 1 to find out the respective definitions of operation in a stack based architecture.
In postfix notation, this will be: AB – CDE * + /. So, the instructions for the program will be as below:
; (A-B), C
; (A-B), C, D
; (A-B), C, D, E
; (A-B), C, (D*E)
; (A-B), (C+(D*E)) ; (A-B) / (C+(D*E))
3. A hypothetical machine has the following characteristics:
034 1501 15 S
Instruction Format
Program Counter (PC) Instruction Register (IR) Accumulator (AC)
Internal CPU Registers
Integer Format
0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory 0011 = Load AC from I/O
0111 = Store AC to I/O
Partial List of Opcodes
The 12-bit address identifies a particular I/O device. Show the program execution steps where the contents (e.g., 03) of the memory word at address 94016 are added to the contents (e.g., 02) of the memory word at address 94116 and the result stored in the latter location 94116.

4. Consider a toy machine with the following details.
The toy machine’s architecture:
The machine has 16 registers numbered 0 through F (in hexadecimal). Each register is two bytes (sixteen bits) long. Similar to MIPS the contents of register 0 is always 0 for this toy machine.
There are 256 cells in the machine’s main memory (addressed from 0x00 to 0xFF). Each cell contains two bytes (sixteen bits) of data.
The machine also has a special 8-bit register as the program counter (PC).
The toy machine’s language:
The machine can support maximum 16 different instructions, which can be used to make changes in the contents of the registers, memory, and PC in specified, well-defined ways. The machine supports two different instruction formats. The instruction formats and the description of the instructions (in Hex notation) are provided in the below diagram:

i. Consider that the memory location 0x00 and 0x01 holds the value 0x0008 and 0x0005 respectively. Write the instructions that will add the contents of these two memory cells, and store the result in the memory cell 0x02.
0x8A00 (Load register location 0xA with the contents from memory location 0x00)
0x8B01 (Load register location 0xB with the contents from memory location 0x01)
0x1CAB (Add the contents of register location 0xA and 0xB, and put the result in register location 0xC)
0x9C02 (Store the computed result to memory location 0x02)
0x0000 (Halt)
ii. Give a single instruction that changes the program counter to memory address 15 regardless of the contents of any registers or memory cells.

5. For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes (opcode) are represented in 8 bits, memory addresses are 64 bits, and register addresses are 6 bits.
For each instruction set architecture shown in Figure above, how many addresses, or names, appear in each instruction for the code to compute C = A + B, and what is the total code size?
// one address appears in the instruction, code size = 8 bits (opcode) + 64 bits (memory address) = 72 bits;
// one address appears in the instruction, code size = 72 bits; Add
// zero address appears in the instruction, code size = 8 bits; Pop C
// one address appears in the instruction, code size = 72 bits; Total code size = 72 + 72 + 8 + 72 = 224 bits.
2) Accumulator
// one address appears in the instruction, code size = 8 bits (opcode) + 64 bits (memory address) = 72 bits;

// one address appears in the instruction, code size = 72 bits; Store C
// one address appears in the instruction, code size = 72 bits; Total code size = 72 + 72 + 72 = 216 bits.
3) Register-memory
Load R1, A
// two addresses appear in the instruction, code size = 8 bits (opcode) + 6 bits (register address) + 64 bits (memory address) = 78 bits;
Add R3, R1, B
// three addresses appear in the instruction, code size = 8 bits (opcode) + 6 bits (register address) + 6 bits (register address) + 64 bits (memory address) = 84 bits;
Store R3, C
// two addresses appear in the instruction, code size = 78 bits;
Total code size = 78 + 84 + 78 = 240 bits.
4) Register-register
Load R1, A
// two addresses appear in the instruction, code size = 8 bits (opcode) + 6 bits (register address) + 64 bits (memory address) = 78 bits;
Load R2, B
// two addresses appear in the instruction, code size = 78 bits;
Add R3, R1, R2
// three addresses appear in the instruction, code size = 8 bits (opcode) + 6 bits (register address) + 6 bits (register address) + 6 bits (register address) = 26 bits;
Store R3, C
// two addresses appear in the instruction, code size = 78 bits;
Total code size = 78 + 78 + 26 + 78 = 260 bits.

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