Exercises for Sections 9 and 10
1. Explain why a hardware interrupt is needed temporarily to force transfer of control away from a running process and back to the OS, at an arbitrarily chosen time.
2. When the OS is running, what privileges must it have to protect itself and user
processes? How might these privileges be implemented?
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3. What are the advantages and disadvantages of reducing the length of a basic time-
4. In programming terms, how does an interrupt routine resemble and how does it
differ from a subroutine?
5. When an interrupt routine begins to run, most CPUs automatically set the interrupt
mask, if one exists. Why?
6. (Harder) In asynchronous I/O under a multitasking OS, when a process requests I/O,
it is not blocked. Therefore, when the I/O completes the OS must signal the process
to let it know and let it take appropriate action. Explain how this might be done.
7. Many caches only cache read cycles. Why is this and why is it usually not seen as a
major limitation? Discuss whether there are circumstances where caching write
cycles would provide some benefit. (Modified from Q2a of S&N May 2021 Exam).
8. Why does it not make sense to allow data read from an input port to be entered into
the cache?
9. Some CPUs have a single-bit output line that informs the external world whether
they are running in system or user mode. Why might this be useful?
Solutions to Exercises for Sections 9 and 10
1. A CPU keeps performing instruction cycles in default sequential order unless it encounters a control instruction that changes that order. In a normal process, if no hardware intervention occurs, this will ensure that the CPU executes only instructions belonging to that process unless it encounters an instruction that causes an exception (like a TRAP or a privileged instruction).
To divert control away from a running process at an arbitrarily chosen time requires an external hardware event which can force an exception. Of such events, only an interrupt is suitable to generate an exception from which the process can still ultimately be resumed, as implied by the word ¡°temporarily¡±. Reset is always unrecoverable while recoverable memory faults only occur when the MMU detects a missing page.
2. The OS must not allow user processes to access the MMU¡¯s internal registers, so that such processes cannot circumvent memory protection. The OS must also prevent user processes from accessing I/O devices directly to ensure these are shared in an orderly fashion. Finally, the OS must prevent a user process from interfering with the system timer to prevent unauthorised alteration to the time slice.
These restrictions can be implemented by only permitting the CPU to select the registers inside the MMU, I/O ports or system timer, when in system mode. If all these devices are in the same physical memory address space as user processes, then the address decoding must not allow user-mode memory cycles to select any of the forbidden components. See Q9 for one way this can be done.
3. If the time slice is too long, the interval between the time slices for a user-interactive process may become so extended that its inactivity while not running becomes obvious to the user, especially if the system is running many tasks. If a time slice is too short, there will be more context switches than necessary and, since each such switch constitutes overhead, while the kernel swaps processes, more CPU time will be wasted on process scheduling, especially saving and restoring state.
4. An interrupt routine is similar to a subroutine in that once it has finished executing, control must return to the instruction after the last one which completed, before the jump to the routine was initiated. The same mechanism can be used to return in both case: this involves pushing the return address onto the stack when the routine is called and popping it when it is ready to return. In both cases any registers used inside the routine should be pushed onto the stack on entry (after the return address) and popped prior to exit: this will prevent the routine from inadvertently altering the internal CPU programmer¡¯s model in an unexpected way.
The main difference is that an ISR is never called by a program instruction within the program but is instead always initiated by a hardware event. A subroutine on the other hand is always called by a calling instruction (like a JAL in Sigma16).
5. Without an interrupt mask set, the device that generated the interrupt could potentially interrupt again before the CPU has had a chance to process the first event. This would not make sense and could cause the first event to be deprioritised.
6. Consider, as an example, an asynchronous output operation to a device D, initiated by a user process, P. To request output, P will execute a TRAP to the OS which will cause the device driver for D to be run in system mode. The driver will contact D and begin the output transfer, using parameters provided by P about, for example, the location and size of the data to be sent to D. However, in asynchronous I/O, P is not blocked but allowed to continue while the I/O operation proceeds. When the output completes, the OS will inform P so that it can respond to the completion.
One common way of doing is for P to be structured by its programmer(s) as a ¡°main¡± routine, PM, which does the non-output work and a separate ¡°output routine¡±, PR which is to run when a requested output operation completes. PM runs by default in P¡¯s time- slice and PR is only ever run after an output finishes. As part of the output request (submitted by the initiating TRAP), the start address of PR is declared to the OS, so the OS knows where to find it when the time comes.
PR has similarities to an ISR (of the sort that might be written for a single-tasking program that handles its own I/O) but, in a multi-tasking OS, a true ISR can only be allowed to run in system-mode (as part of a device driver). PR is not initiated directly by a hardware interrupt from D, but is started by the OS, when the output operation is complete, and then runs in P¡¯s time-slice, instead of PM. It continues to run instead of PM until it completes and returns control to PM in the same way as a real ISR would.
7. When reading the same item twice, the CPU will find it in the cache, saving time; however, when writing an item twice it would normally need to be stored into both the cache and primary memory each time. This reduces the benefit of caching (although it will still help next time the same item is read). Note: some (so-called write-back) caches try to defer updates of primary memory but this is harder to implement and increases complexity.
Reading is also much more common than writing because instruction fetches are all read operations and loops always cause the same instructions to be fetched multiple times. So, the commonest cache hits are typically instruction fetches in loops. Writing is only relevant when data is stored (e.g. in Sigma16, only on the third memory cycle of a STORE) which is a significantly rarer event.
8. The point about a cache is that it allows the CPU to avoid fetching the same content from the same address more than once, thus saving time. However, the registers in an input port change their content every time new data is input from a peripheral: this is completely different from a normal primary memory location which will not change its content unless the CPU writes to it. An input operation can only be successful if no data is lost or duplicated. If the CPU reads from its cache instead of from the input port, it will not be reading the latest input data item (the cache entry is then said to have gone
stale). Worse, it will continue to read that first input item repeatedly instead of all subsequent ones, which will be overwritten and lost.
9. When the CPU is in user mode it should not be allowed to access registers in the MMU, the timer or I/O ports. In fact, all that is required for full protection is to force all user-mode memory addresses to be translated by the MMU (this will protect the other components too). A hardware line from the CPU, indicating the mode currently in use can be fed to the MMU to prevent it from allowing its registers to be accessed unless system mode is indicated.
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