Digital Logic and Computer Systems
Final Exam
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Friday, December 4th, 2020
08:30 PM – 10:20 PM
Name: ______________________________________
Student ID: _________________________________
Instructions
• This exam will be proctored on Zoom. If you are not in Zoom from exam begin to submission, you will not
receive a grade.
• This is a completely open-note exam, including online resources; however, collaboration between other
students is strictly prohibited.
• Submission will be via Canvas as a PDF/document upload.
• Any form of taking this exam is acceptable. You may print it, write on notebook/copy paper, use a tablet-stylus
combination, etc. If you do not print it, clearly mark which question you are on.
• Ensure ALL work is visible and clearly legible! Write large and dark. Please circle answers where appropriate.
• This is a 7-page exam, including this title sheet. There are no blank pages (all pages have a question).
Problem 1 Problem 2 Problem 3 Problem 4 Total
/19 /15 /10 /20 /64, %
EEL 3701C – Final Exam Friday December 4th, 2020 8:30 PM – 6:020 PM
Problem I (Warming Up, 20 pts)
1. Explain why sign extension of the immediate is necessary in the MIPS Datapath (2 pts)
2. In MIPS, why must all accessed memory addresses be multiples of 4? (2 pts)
3. Explain the difference between little endian vs big endian (2 pts)
4. In a circuit where multiple components can output onto a single wire, name one example of a component that
can solve the issues that may arise when two or more components drive the same wire? (1 pts)
5. What is the potential use of a demultiplexer in a system? Provide an example (1 pts)
6. A processor must always consist of a both a datapath and control path. True or False? (2 pts)
7. The control path of any existing processor must be a finite state machine with at least 2 states. True or False?
EEL 3701C – Final Exam Friday December 4th, 2020 8:30 PM – 6:020 PM
8. Any Datapath that implements addition and subtraction must provide an adder and a subtracter separately.
True or False? Explain. (Hint: How else can subtraction be represented in binary operations?) (2 pts)
9. Explain the difference between the following memory types
a. RAM and ROM (1 pts)
b. OTP-ROM and EEPROM (1 pts)
10. EPROM is more convenient to use than EEPROM. True or False? Explain. (1 pts)
11. What is a decoder? Provide an application of a decoder (2 pts)
EEL 3701C – Final Exam Friday December 4th, 2020 8:30 PM – 6:020 PM
Problem II (RTL, Arithmetic 15 pts)
1. Use the Shift-and-Add algorithm to multiply the following numbers in two’s complement:
X = -7 and Y = -12. Use the fewest number of bits possible. Do not swap X and Y. (10 pts)
(continued on next page)
EEL 3701C – Final Exam Friday December 4th, 2020 8:30 PM – 6:020 PM
2. How many total additions were required to complete the previous multiplication? How many bits would the
adder circuit portion of the Shift-and-Add system have? (2 pts)
3. Calculate the lower bound of the total time required to perform the prior multiplication for the following two
cases. Let the gate delay be 10ns. Assume that comparison and shift operations are negligible. Do not consider
the frequency of the clock in your calculations.
a. Execution-time with ripple-carry implementation (1.5 pts).
b. Execution-time with carry-lookahead implementation (1.5 pts).
EEL 3701C – Final Exam Friday December 4th, 2020 8:30 PM – 6:020 PM
Problem III (Memory, 10 pts)
Sketch the internal design of a 7×6 OTP-ROM built from one or more 4×4 OTP-ROMs. The technology uses fuses (as
opposed to programmable interconnects). Include all necessary internal components.
Configure the ROM to hold the following address/value pairs. Anything not specified are don’t cares.
Address 0 3 5 6
Value 1 6 10 0
EEL 3701C – Final Exam Friday December 4th, 2020 8:30 PM – 6:020 PM
Problem IV (MIPS ISA, Assembler, 20 pts)
1. Assuming that N is stored in register $s3. Array A is stored in a memory and its address is in register $s4. Provide
the MIPS assembler code for the following pseudo code. Use a custom instruction END to indicate your code
is complete. (16 pts)
Table provided for convenience. More lines are provided than necessary.
2. Furthermore, describe what you would change about your code if we told you that the memory of this processor is
half-word (16 bits) aligned, and a read operation returns a half-word. Also, registers are a half-word large to
accommodate this change.
Assume “normal” MIPS requirements of word-aligned memory addresses have been modified for the changes
Assume that the array in memory now contains one element per half-word (i.e., each item in the array is now only
16-bits large).
Describe below what must you change about the code you wrote above? Hint: This should be a very simple change.
Line # Label Instruction Line # Label Instruction
FOR (i=0; i < N; i++) IF (i < 7) A[i] = A[i] + 2 A[i] = A[i] - 10 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com