CS代考 CS2305: Computer Architecture

CS2305: Computer Architecture
Multi-cycle Processor
(Computer Organization: Chapter 4

Copyright By PowCoder代写 加微信 powcoder

Department of Computer Science and Engineering

Fundamentals
Recap: A Summary of Control Signals
inst Register Transfer
ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub” Fundamentals The Complete Single Cycle Data Path with Control 6 Instr<31:26>
RegDst ALUSrc
3 func Instr<5:0> 6
Main Control
Branch Jump
Instruction<31:0>
Rt Rs Rd Imm16
Rw Ra Rb 32 32-bit Registers
Zero MemWr 32
Data Memory
imm16 16 Instr<15:0>
ALU Control
Instruction Fetch Unit
<0:15> <11:15>
<16:20> <21:25>

Fundamentals
Creating a Single Datapath from the Parts
p Assemble the datapath segments and add control lines and multiplexors as needed
p Single cycle design – fetch, decode and execute each instructions in one clock cycle
m no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders)
m multiplexors needed at the input of shared elements with control lines to do the selection
m write signals to control writing to the Register File and Data Memory
p Cycle time is determined by length of the longest path

Fundamentals
Clocking Methodology
Setup Hold Setup Hold
p All storage elements are clocked by the same clock edge
p Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew
Don’t Care

Fundamentals
Instruction Critical Paths
q Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires, setup and hold times) except:
Instruction and Data Memory (200 ps) ALU and adders (100 ps)
Register File access (reads or writes) (50 ps)

Fundamentals
Fetch, R, and Memory Access Portions
Instruction Memory
Read Address
ALU control
Read Addr 1 Register Read
Instruction
Read Addr 2
Read Data 2
Write Addr Write Data
Memory ReadData
Write Data
16 Extend 32

Fundamentals
Time Delay for LW: Critical Path
Rs, Rt, Rd, Op, Func
ALUctr ExtOp ALU Reg RegWr
busA busB Address busW

Delay through Extender & Mux
Instruction Memory Access Time

Delay through Control Logic
Data Memory Access Time

Write Occurs
Register File Access Time

Fundamentals
What’s wrong with our CPI=1 processor?
Arithmetic & Logical
Store Branch
Critical Path
Inst Memory
Inst Memory
Inst Memory
Inst Memory

Fundamentals
Single Cycle Disadvantages & Advantages
p Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction
m especially problematic for more complex instructions like floating point multiply
Cycle 1 Cycle 2
p May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle
p But is simple and easy to understand

Fundamentals
Multicycle Implementation Overview
p Each instruction step takes 1 clock cycle
m Therefore, an instruction takes more than 1 clock cycle to
p Not every instruction takes the same number of clock cycles to complete
p Multicycle implementations allow
m faster clock rates
m different instructions to take a different number of clock cycles
m functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result
n only need one memory
n only need one ALU/adder

Fundamentals
The – A High Level View
p Registers have to be added after every major functional unit to hold the output value until it is used in a subsequent clock cycle
(Instr. or Data) ALU Write Data
Read Addr 1 Register Read
Read Addr 2
Read Data 2
Write Addr Write Data

Fundamentals
Clocking the
System Clock
clock cycle
Read Data (Instr. or Data)
Write Data
Read Addr 1 Register Read
Read Addr 2
Read Data 2
Write Addr Write Data

Fundamentals
Our Multicycle Approach
p Break up the instructions into steps where each step takes a clock cycle while trying to
m balance the amount of work to be done in each step m use only one major functional unit per clock cycle
p At the end of a clock cycle
m Store values needed in a later clock cycle by the current instruction in a
state element (internal register not visible to the programmer)
n IR – Instruction Register
n MDR – Memory Data Register
n A and B – Register File read data registers n ALUout–ALUoutputregister
n All (except IR) hold data only between a pair of adjacent clock cycles (so they don’t need a write control signal)
m Data used by subsequent instructions are stored in programmer visible state elements (i.e., Register File, PC, or Memory)

Fundamentals
The Complete with Control
PCWriteCond
MemRead MemWrite
MemtoReg IRWrite
ALUSrcB ALUSrcA
RegWrite RegDst
Instr[25-0]
Shift left 2
Read Data (Instr. or Data)
Write Data
Read Addr 1
Register Read
Read Addr 2
Write Addr Write Data
Read Data 2
Instr[15-0] Instr[5-0]
Sign Extend 32
Shift left 2
ALU control
Instr[31-26]

Fundamentals
Our Multicycle Approach, con’t
p Reading from or writing to any of the internal registers, Register File, or the PC occurs (quickly) at the beginning (for read) or the end of a clock cycle (for write)
p Reading from the Register File takes ~50% of a clock cycle since it has additional control and access overhead (but reading can be done in parallel with decode)
p Had to add multiplexors in front of several of the functional unit input ports (e.g., Memory, ALU) because they are now shared by different clock cycles and/or do multiple jobs
p All operations occurring in one clock cycle occur in parallel
m This limits us to one ALU operation, one Memory access, and one Register File access per clock cycle

Fundamentals
Five Instruction Steps
1) Instruction Fetch
2) Instruction Decode and Register Fetch
3) R-type Instruction Execution, Memory Read/Write Address Computation, Branch Completion, or Jump Completion
4) Memory Read Access, Memory Write Completion or R-type Instruction Completion
5) Memory Read Completion (Write Back) INSTRUCTIONS TAKE FROM 3 – 5 CYCLES!

Fundamentals
RTL for Instructions
p Common Steps:
m Instr fetch IR = Memory[PC]; mPC Updating PC = PC + 4;
p Decode and Register reading m A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
q Instruction Dependent operation

Fundamentals
RTL Summary
Instr fetch
IR = Memory[PC];
PC = PC + 4;
A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
ALUOut = PC +(sign-extend(IR[15-0])<< 2); A + sign-extend (IR[15-0]); Memory access MDR = Memory[ALUOut]; or Memory[ALUOut] = B; Write- back Reg[IR[20-16]] Fundamentals Multi-cycle datapath PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Instr[25-0] left 2 2 Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Step 1: Instruction Fetch p Use PC to get instruction from the memory and put it in the Instruction Register p Increment the PC by 4 and put the result back in the PC p Can be described succinctly using the RTL "Register- Transfer Language“ IR = Memory[PC]; PC = PC + 4; Can we figure out the values of the control signals? What is the advantage of updating the PC now? Fundamentals Datapath Activity During Instruction Fetch PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Shift left 2 Instr[25-0] Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Signals Settings Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 IorD=0 MemRead;IRWrite Fetch ALUsrcB=01 PCSource,ALUOp=00 Fundamentals Step 2: Instruction Decode and Register Fetch p Don’t know what the instruction is yet, so can only m Read registers rs and rt in case we need them m Compute the branch address in case the instruction is a branch p The RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC+(sign-extend(IR[15-0])<< 2); p Note we aren't setting any control lines based on the instruction (since we don’t know what it is (the control logic is busy "decoding" the op code bits)) Fundamentals Datapath Activity During Instruction Decode PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Instr[25-0] Shift left 2 Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Decode Control Signals Settings Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 MemRead;IRWrite ALUsrcB=01 PCSource,ALUOp=00 ALUSrcB=11 PCWriteCond=0 Fundamentals Step 3 Instruction Dependent Operations p ALU is performing one of four functions, based on instruction type p Memory reference (lw and sw): ALUOut = A + sign-extend(IR[15-0]); ALUOut = A op B; if (A==B) PC = ALUOut; PC = PC[31-28] || (IR[25-0] << 2); Fundamentals Datapath Activity During lw & sw Execute PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Instr[25-0] Shift left 2 Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Datapath Activity During R-type Execute PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Instr[25-0] Shift left 2 Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Datapath Activity During beq Execute PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Instr[25-0] Shift left 2 Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Datapath Activity During j Execute PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Shift left 2 Instr[25-0] Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Execute Control Signals Settings IorD=0 MemRead;IRWrite Instr ALUSrcB=11 PCWriteCond=0 PCSource=10 Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 ALUsrcB=01 PCSource,ALUOp=00 ALUSrcB=00 ALUSrcB=10 PCWriteCond=0 ALUSrcB=00 PCWriteCond=0 PCSource=01 PCWriteCond (Op = R-type) (Op = lw or sw) (Op = beq) Fundamentals Step 4 (also instruction dependent) p Memory reference: MDR = Memory[ALUOut]; Memory[ALUOut] = B; -- lw -- sw p R-type instruction completion Reg[IR[15-11]] = ALUOut; p Remember, the register write actually takes place at the end of the cycle on the clock edge Fundamentals Datapath Activity During lw Memory Access PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Shift left 2 Instr[25-0] Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Datapath Activity During sw Memory Access PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Shift left 2 Instr[25-0] Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Datapath Activity During R-type Completion PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Shift left 2 Instr[25-0] Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Memory Access Control Signals Settings Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 IorD=0 Instr MemRead;IRWrite ALUSrcB=11 PCWriteCond=0 PCSource=10 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 (Op = lw) ALUsrcB=01 PCSource,ALUOp=00 ALUSrcB=00 ALUSrcB=00 Execute Memory PCWriteCond=0 PCSource=01 PCWriteCond MemtoReg=0 PCWriteCond=0 MemRead AccessMemWrite IorD=1 IorD=1 PCWriteCond=0 PCWriteCond=0 (Op = R-type) (Op = lw or sw) (Op = beq) Fundamentals Step 5: Memory Read Completion (Write Back) p All we have left is the write back into the register file the data just read from memory for lw instruction Reg[IR[20-16]]= MDR; What about all the other instructions? Fundamentals Datapath Activity During lw Write Back PCWriteCond IorD MemRead MemWrite MemtoReg ALUSrcB ALUSrcA RegWrite RegDst Instr[25-0] Shift left 2 Read Data (Instr. or Data) Write Data Read Addr 1 Register Read Read Addr 2 Read Data 2 Write Addr Write Data Instr[15-0] Sign Extend 32 Instr[5-0] Shift left 2 ALU control Instr[31-26] Fundamentals Write Back Control Signals Settings Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 MemRead;IRWrite Instr ALUSrcB=11 PCWriteCond=0 PCSource=10 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 (Op = lw) ALUsrcB=01 PCSource,ALUOp=00 ALUSrcB=00 ALUSrcB=00 Execute Memory PCWriteCond=0 PCSource=01 MemtoReg=1 PCWriteCond=0 PCWrite Read AccessMemWrite IorD=1 IorD=1 PCWriteCond=0 PCWriteCond=0 MemtoReg=0 PCWriteCond=0 Write Back (Op = R-type) (Op = lw or sw) (Op = beq) Fundamentals RTL Summary Instr fetch IR = Memory[PC]; PC = PC + 4; A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2); A + sign-extend (IR[15-0]); Memory access MDR = Memory[ALUOut]; or Memory[ALUOut] = B; Write- back Reg[IR[20-16]] Fundamentals 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com