DESN2000: Engineering Design & Professional Practice (EE&T)
Data processing operations and memory access
School of Electrical Engineering & Telecommunications Graduate School of Biomedical Engineering
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Biomedical Microsystems Lab
ARM data processing operations
• Arithmetic instructions
• Data move instructions
• Logic instruction
• Shifts and rotate options
• Multiplication
Memory access instructions
• Load-store architecture
• ARM load and store operations
• Addressing modes
• Load / store in byte and halfword levels
• Endianness
• Load and store multiple
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ARM data processing instructions
• Data processing instructions:
• Arithmetic operations
• Comparison
• Logical operations
• Data movement
ADD, SUB, ADC,… CMP, CMN, TST, TEQ AND, EOR, ORR, BIC,… MOV, MVN
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ARM data processing instructions
• 4-field instruction format:
• source 1
• source 2
name of the operation
destination; a register
1st source; a register
2nd source; a register, shifted register, or an immediate
• Source 2 – shifted register: Shifting amount can be:
• Immediate value: 5-bit unsigned number
add a1, v1, v3, lsl #3
• Specified in the lowest-8-bits of another register
add a1, v1, v3, lsl v4
• Source 2 – immediate:
• Must be representable by an 8-bit number, optionally right-rotated an even number of bits:
add a1, v1, #5 ; permitted add a1, v1, #0xFE00 ; permitted add a1, v1, #0xFEA3 ; not permitted
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Arithmetic instructions: add / subtract
Examples: assuming variables A, B, C, D, E correspond to registers V1, V2, V3, V4, V5, respectively.
• E=(A+B)−(C+D)
ADD V5, V1, V2
ADD A1, V3, V4 ; use intermediate register A1 SUB V5, V5, A1
• E = (A+B+C)−2×D
ADD V5, V1, V2
ADD V5, V5, V3
SUB V5, V5, V4, LSL #1
• E = −A = 0 − A (use reverse subtraction, RSB)
RSB V5, V1, #0
Program Status Register
• Use ADDS, SUBS if you want to save the condition code flags.
• Both CPSR and SPSR have the following format
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Do not modify / Read as Zero
• Bit [31:28] – conditional flags
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– N – Negative
Arithmetic instructions: add / subtract
• Add /subtract with carry:
• Examples:
ADCV1,V2,V3 ;V1=V2+V3+C SBCV1,V2,V3 ;V1=V2+!V3+C RSCV1,V2,V3 ;V1=V3-!V2+C
• Useful for 64-bit arithmetic.
add with carry
subtract with carry reverse subtract with carry
Using adder circuit for subtraction: A – B = A + not(B) + 1
Setting carry with subtraction:
If A ≥ B ⇒ C=1
If A < B ⇒ C=0
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Arithmetic instructions: add / subtract
64-bit addition:
64-bit subtraction:
64*bit#number#1# 64*bit#number#2#
64'bit#number#1# 64'bit#number#2#
Difference#
ADDS R4, R0, R2 ADC R5, R1, R3
SUBS R4, R0, R2 SBC R5, R1, R3
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Data move instructions
• Moving data between regs?
ADDV1,V2,#0 ;V1 ← V2
• Alternatively, MOV instruction can be used.
MOVV1,V2 ;V1 ← V2
• The second operand can be an immediate (8-bit constraint), register or a shifted
• Wait a jiffy (no-operation; nop)?
MOV V1, V1
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Data move instructions
• MVN (move negative) moves the complement of the source operand into the
destination register.
MOV V1, #0xA3 ; V1 = 0x000000A3 MVN V2, V1 ; V2 = 0xFFFFFF5C
• MVN can be used to load -1 into a register.
MVN V1, #0 ; V1 = 0xFFFFFFFF = -1
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Logical instructions
Logic instructions perform bit-wise logical operations associated with registers: AND, ORR, EOR, BIC
Instruction format:
name of the operation
destination operand (register)
1st source, a register
2nd source, a register, shifted register, or an immediate
AND V1, V2, V3
AND V1, V2, V3, LSL #2 AND V1, V2, V3, LSL A1
AND V1, V2, #0xF3
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Logical instructions: AND
• ANDV1,V2,V3 ⇒ V1=V2ANDV3
A AND 0 = 0
A AND 1 = A
• Bit-wise AND operation can be used to create a bit-mask.
• Example: if register V1 contains:
1011 0110 1011 1001 1010 1110 0110 1010
to extract bits 4-11, we can use the following mask: 0000 0000 0000 0000 0000 1111 1111 0000
AND V1, V1, #0xFF0
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Logical instructions: BIC
• Bit clear (BIC) is used to set certain bits to zero (and leaving other bits unchanged) in a register.
• BICV1,V2,V3 ⇒ V1=V2AND(NOTV3)
• Bits of source-1 operand (V2) in places where source-2 operand (V3) has ones will be
• Example: suppose V1 has:
1010 1100 1010 0001 1000 0011 1100 1110
To isolate the upper 24 bits of V1, can do a bit-clear with mask 0000 0000 0000 0000 0000 0000 1111 1111
BIC V1, V1, #0xFF
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Logic Instruction – ORR, EOR
• ORR: bit-wise logical OR operation
• EOR: bit-wise logical XOR operation
• Recall: AOR0 =A
A XOR 1 = NOT A A XOR 0 = A AXORA= 0
ORR V1, V1, #0xFF
ORR V1, V1, V2
ORR V1, V1, V2, LSL #2 ORR V1, V1, V2, LSL V3
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Shift and rotate operations
• Shifting operation is embedded in almost all data processing instructions.
• Performed by the barrel shifter in the data path.
• ARM shift and rotate operations:
Logical shift to the left Logical shift to the right Arithmetic shift to the right Rotate right
Rotate right through carry
ARM Thu On-c Debu Multi Embe ICE (
• Only source-2 operand can be shifted. The shifting amount is specified as an immediate (5 bits) or in another register.
THE PROCESSOR (ARM7TDMI
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Shift and rotate operations
• Logical shift left (LSL) examples:
mova1,v1,lsl#8 ;a1:=v1<<8-bit mova1,v1,lslv2 ;a1:=v1<
1001 0010 0011 0100 0101 0110 0111 1000 0000 0000 0101 0110 0111 1000 0000 0000
• Sets C to the value of the last bit to fall off the end of the shift. But this detail is not often significant.
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Shift and rotate operations
• Arithmetic shift right (ASR) examples:
mova1,v1,asr#8 ;a1:=v1>>8-bits ; a1[31:24] := v1[31]
1001 0010 0011 0100 0101 0110 0111 1000 1111 1111 1001 0010 0011 0100 0101 0110
0001 0010 0011 0100 0101 0110 0111 1000 0000 0000 0001 0010 0011 0100 0101 0110
mova1,v1,asrv2 ;a1:=v1>>v2-bits ; a1[31:24] := v1[31]
Sign bit shifted in
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Shift and rotate operations
• Rotate right (ROR) examples:
mova1,v1,ror#8 ;a1:=v1>>8-bits ; a1[31:24] := v1[7:0]
1001 0010 0011 0100 0101 0110
1001 0010 0011 0100 0101 0110
mova1,v1,rorv2 ;a1:=v1>>v2-bits
; a1[31:(31-v2)] := v1[v2:0]
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Shift and rotate operations
• Rotate right through carry (RRX) example:
mova1,v1,rrx ;a1:=v2>>1-bit ; a1[31] := C-flag
; C-flag := v1[0]
• Rotation happens through the carry flag in CPSR. Rotate by 1-bit only.
Rotate right thru carry bit
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Shift and rotate operations
Q: Isolate the second byte of register V1 and move it to the first byte of V1.
Option 1: by bit-masking then shifting
AND V1, V1, #0xFF00 MOV V1, V1, LSR #8
Option 2: shift left (zero-fill right) then shift right (zero-fill left)
MOV V1, V1, LSL #16 MOV V1, V1, LSR #24
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Multiplication
• Multiplication is expensive (clk cycles, power and circuit complexity).
• Multiplication by a constant may be achieved by shifting and add / sub.
• Examples: assuming variables A and B corresponds to registers V1 and V2, respectively.
1. B=5×A=(22 +1)A=22A+A ADD V2, V1, V1, LSL #2
2. B=105×A=(15×7)A=(24 −1)(23 −1)A RSB V2, V1, V1, LSL #4
RSB V2, V2, V2, LSL #3
• Reverse subtract without carry, syntax:
RSB
Rd = operand2 – Rn
Useful because ALU operations permissible on operand2.
• 24 – 1 achieved by LSL #4, then RSB reverse-subtracting 1.
• 23 – 1 achieved by LSL #3, then RSB reverse-subtracting 1.
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Load-store architecture
• Data processing instructions only work on registers.
Must move memory-based data to register first, before processing.
• Remember:
• Memory is organized as 8-bit blocks
• Registers are 32-bits wide.
• 32-bit data bus and 32-bit address bus.
! Processor!Core!
Registers!
! Data/Program!
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Addressing modes
• Pre-indexed ++address
• offset is added to the base register before the load / store.
• The load/store takes place at the address pointed by (base + offset).
• Optionally updates the base register with new address.
• Post-indexed address++
• offset is added to the base after the load / store.
• The load/store happens at the address pointed by the base register.
• Always updates the base register with new address.
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Pre-indexed load / store
Syntax:
Load/store operation happens at the effective address (rn + offset).
• opcode • Cond
• Offset • !
LDR (loading a word) and STR (storing a word). Optional conditional execution.
Destination register for LDR and source register for STR. Base register.
Offset from the base register: an immediate, a register, or a shifted register. Optionally write effective address (base + offset) back to the base register.
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Pre-indexed load / store – examples
• LDR V1, [V2, #12]
A word located at the effective address V2 + 12 is loaded into register V1.
• LDR V1, [V2, #12]!
A word located at the effective address V2 + 12 is loaded into register V1 and the base register V2 is updated to V2 + 12.
• LDR V1, [V2, V3]
A word located at the effective address V2 + V3 is loaded into register V1.
• LDR V1, [V2, V3, LSL #2]!
A word located at the effective address V2 + 4*V3 is loaded into register V1 and the base register V2 is updated to V2 + 4*V3.
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Post-indexed load / store
cond}
LDR (loading a word) and STR (storing a word).
Optional conditional execution.
Destination register for LDR and source register for STR.
Base register. The address where load/store occurs.
Added to base after load/store: immediate, register, or a shifted register.
Load/store happens at the address rn
(rn + offset) becomes the base register for the next load/store.
• Opcode • Cond
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Post-indexed load / store – examples
• LDR V1, [V2], #12
A word located at the effective address given by V2 is loaded into register V1, then base register V2 is updated to V2 + 12.
• LDR V1, [V2], V3
A word located at the effective address given by V2 is loaded into register V1, then base register V2 is updated to V2 + V3.
• LDR V1, [V2], V3, LSL #3
A word located at the effective address given by V2 is loaded into register V1, then base register V2 is updated to V2 + 8*V3.
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Load / store examples – C to assembly
• CompileCcode:C=A+B
• All variables are integers (words) located in memory locations having the following offsets from the base address 0x4000:
A: offset*0
B: offset*4
C: offset*8
MOV V1, #0x4000 LDR V2, [V1] LDR V3, [V1, #4] ADD V2, V2, V3 STR V2, [V1, #8]
; base address in V1 ; load A
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Load / store examples – C to assembly
Compile C code: G = F + my_array[i]
All variables are integers. G and F correspond to registers V1 and V2, respectively. Base address for my_array (i.e. address of my_array[0]) is in register V3. Array index i is in register V4.
Using pre-indexed addressing:
LDR A1, [V3, V4, LSL #2] ADD V1, V2, A1
Using post-indexed addressing:
; load my_array[i] ; perform addition
ADD V3, V3, V4, LSL #2
LDR A1, [V3] ; load my_array[i]. V3 now points to my_array[i] ADD V1, V2, A1 ; perform addition
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Load / store in byte & halfword
Load/store can happen at halfword or byte level.
• Variants of load: • LDR
• LDRSB • LDRH
loading a word
loading a byte
loading a signed byte loading a halfword loading a signed halfword
Variants of store:
• STRB • STRH
storing a word storing a byte storing a halfword
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Load / store in byte & halfword
• This loads / stores the register’s least-significant-byte.
• Example: loading a byte from memory to a register.
LDRB A1, [V1, #2] ; V1 + 2-byte offset LDRB A1, [V1, V2]
LDRB A1, [V1, V2, LSL #1] ; OK, V1 + V2*2
• Use STRB to store.
Register Memory Register
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Load / store in signed byte & halfword
• Performs automatic sign bit extension
• Example: loading a signed byte from memory to a register.
LDRSB A1, [V1, #2] ; V1 + 2-byte offset LDRSB A1, [V1, V2]
LDRSB A1, [V1, V2, LSL #1] ; illegal, not supported
Register Memory FF FF FF
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Load / store in byte & halfword
Compile C code: G = F + my_array[8]
G and F correspond to registers V1 and V2, respectively. Base address for my_array
(i.e. address of my_array[0]) is in register V3 and my_array is of type unsigned char. LDRB A1, [V3, #8]
ADD V1, V2, A1
Compile C code: G = F + my_array[8]
G and F correspond to registers V1 and V2, respectively. Base address for my_array (i.e. address of my_array[0]) is in register V3 and my_array is of type char.
LDRSB A1, [V3, #8] ADD V1, V2, A1
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Load / store in byte & halfword
Compile C code: G = F + my_array[8]
G and F correspond to registers V1 and V2, respectively. Base address for my_array
(i.e. address of my_array[0]) is in register V3 and my_array is of type unsigned short.
LDRH A1, [V3, #16] ADD V1, V2, A1
“short” is twice the size of “char” so offset twice the amount (8 x 2 = 16)
Compile C code: G = F + my_array[8]
G and F correspond to registers V1 and V2, respectively. Base address for my_array
(i.e. address of my_array[0]) is in register V3 and my_array is of type short. LDRSH A1, [V3, #16]
ADD V1, V2, A1
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Endianness
• Specifies the order of bytes stored in the memory.
• Little-endian: the least significant byte of register is stored at the lowest memory address.
• Big-endian: the least significant byte of register is stored at the highest memory address.
• ARM is little-endian by default.
C2″ B1″ A0″ A0″
Memory” Register”
Memory” Register”
0x400″ B1″ 0x401″ C2″ 0x402″ D3″ 0x403″
D3″ 0x400″ C2″ 0x401″ B1″ 0x402″ A0″ 0x403″
Li9le;endian”configuraBon”
Big;endian”configuraBon”
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Assembly examples
Adding elements in an array
Let A[ ] be an integer array (each element is 32 bits). The base address (i.e. the address of A[0]) is in register A1. Compute:
x+Xn 1 A[i]
and store the result in register V1. Starting index x is in register A2 and number of
terms n ≥ 2 is stored in register A3. You should use post-indexed addressing mode.
ADD A1, A1, A2, LSL #2 ADD A3, A1, A3, LSL #2 MOV V1, #0
LDR A4, [A1], #4
ADD V1, V1, A4
CMP A1, A3
; address of A[x] … start ; address of A[x+n] … end ; initialize the sum
; load A[i++]
; summation
; check whether i=x+n ; repeat while i