ECE391- Computer System
Engineering
Programable Interrupt Controller
Copyright By PowCoder代写 加微信 powcoder
University of Illinois at Urbana- Champaign
Announcements
• PS2 Posted – Committed to the master (main)
branch on GitLab by 5:59PM on 9/21
• MP2 Posted – All checkpoints should be committed
to the master(main) branch on GitLab by:
• Checkpoint 1: 5:59PM on 10/5
• Final Checkpoint: 5:59PM on 10/12
ECE391 EXAM 1
• EXAM I – Wednesday, September 29th, 7:00pm-
• Location: ECEB 1002
• Online details to follow, but expect it to be
proctored and at same time.
• NO Lecture on Tuesday, September 28
• Review Session
Topics covered by EXAM 1
• Material covered in lectures (Lecture1 – Lecture10)
• x86 Assembly
• C (e.g., Calling Convention)
• Synchronization
• Interrupt control (using PIC)
• Material covered in discussions
Lecture Topics
• Programmable interrupt controller (PIC)
• motivation & design
• hardware for x86
• Linux abstraction of PIC
PIC Motivation and Design
• How do we connect devices to the processor’s
interrupt input?
• An OR gate? why not?
interrupt?
(INTA)’x86
PIC Motivation and Design (cont.)
• who writes the vector # ?
• possible to build arbiter, but…
• what if more than one raised interrupt?
• extra work for processor to query all devices
• must execute interrupt code for device that raised interrupt
• could have been more than one device
• no way to tell with OR gate
• not all devices support query
• many devices too simplistic to support query
• and operations (e.g., reading from port) may not be idempotent
• might be nice to have concept of priority and preemption,
i.e., interrupting an interrupt handler
8259A Programmable Interrupt
Controller (PIC)
Intel 8259
[images: Wikipedia users German, Nixdorf]
Logical Model of PIC Behavior
• Watch for interrupt signals
• up to eight devices
• one interrupt line each
Logical Model of PIC Behavior
• Track which devices/input lines are currently in
service by processor
• i.e., processor is executing interrupt handler for that
• using internal state
Logical Model of PIC Behavior
• When a device raises an interrupt
• If priority is higher than those of in-service interrupts
• report the highest-priority raised to the processor
• mark that device as being in service
• do nothing
Logical Model of PIC Behavior
• When processor reports EOI (end of interrupt) for
some interrupt
• remove the interrupt from the in-service mask
• check for raised interrupt lines that should be reported
to processor
Logical Model of PIC Behavior
• Protocol for reporting interrupts
• PIC raises INTR
• processor strobes INTA’ (active low) repeatedly
• creates cycles for PIC to write vector to data bus
• (must follow spec timing! PIC is not infinitely fast!)
• processor sends EOI with specific combinations of A & D
inputs (A is from address bus, D is from data bus)
Logical Model of PIC Behavior
• What about A, CS’, RD’, and WR’ ?
• A = address match for ports
• CS’ = chip select (does processor want PIC to
read/write?)
• RD’ and WR’ defined from processor’s point of view
• RD’ = processor will read data (vector #) from PIC
• WR’ = processor will write data (command, EOI) to PIC
Logical Model of PIC Behavior
• Map to ports 0x20 & 0x21
• given ADDR bus
• logic to form A and CS’ inputs to PIC
• Remember
• the PIC is asynchronous!
• all interactions have timing constraints
• see specifications for details
to A on PIC
≠ 0x10ADDR[0]
ADDR[15:1]
Logical Model of PIC Behavior
Logical Model of PIC Behavior (cont.)
• Are eight devices enough? No? What then?
• hook 2, 3, or 4 PICs to processor?
• [same problem as before!]
• design a big PIC?
• [waste of transistors; not cheap in 8259A era]
• design several PICs?
• [waste of humans! (and production costs)]
• Better answer: cascade
slave slave. . .
devices (up to 64)
Cascade Configuration of PICs
Cascading (cont.)
• Previous figure showed x86 configuration of two
• master 8259A mapped to ports 0x20 & 0x21
• slave 8259A mapped to ports 0xA0 & 0xA1
• slave connects to IR2 on master
• Question
• prioritization on 8259A: 0 is high, 7 is low
• what is prioritization across all 15 pins in x86 layout?
• (highest) M0…M1…S0…S7…M3…M7 (lowest)
Cascading (cont.)
• Which PIC should write interrupt vector when
when processor strobes INTA’?
• Slave doesn’t know which interrupt master reported to
• Master doesn’t know which device connected to slave
raised the slave INT line.
• Master tells which slave they should write
• CAS bus transmits number (3-bits)
• SP for differentiating between master and slave
Cascading (cont.)
• In Linux (initialization code to be seen shortly)
• master IR’s mapped to vector #’s 0x20 – 0x27
• slave IR’s mapped to vector #’s 0x28 – 0x2F
• remember the IDT?
Interrupt Descriptor Table
Linux 8259A Initialization
Comments on Linux’ 8259A
Initialization Code
• What is the auto_eoi parameter?
• always = 0, not used in Linux
• Four initialization control words to set up the master
• Four initialization control words to set up the slave
• ICW1 0 start init, edge-triggered inputs,
cascade mode, 4 ICWs
• ICW2 1 high bits of vector #
• ICW3 1 master: bit vector of slaves; slave:
input pin on master
• ICW4 1 ISA=x86, normal/auto EOI
Comments on Linux’ 8259A
Initialization Code (cont.)
• What does the “_p” mean on the “outb” macros?
• add PAUSE instruction after OUTB; “REP NOP” prior to P4
• delay needed for old devices that cannot handle
processor’s output rate
• Critical section spans the whole function; why?
• avoid other 8259A interactions during initialization sequence
• (device protocol requires that four words be sent in order)
• Why use _irqsave for critical section?
• this code called from other interrupt initialization routines
• which may or may not have cleared IF on processor
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