Hardware Verification Marking Schedule
For the hardware verification coursework, the marks will be distributed across the deliverables
listed here, with 20% of the marks reserved for assessing how well your verification covers the
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functionality.
• ReadMe and Verification Plan – 10
• Modified RTL code for the GPIO and the dual lock-step configuration of the VGA Peripheral –
• SystemVerilog files of your testbench(es) – 20
• SystemVerilog assertions and evidence of trying to prove some of these with formal
verification – 15
• Evidence of running the unit-level testbench simulation – 5
• Assembler (or C) code for your top-level integration testing – 5
• If possible, a log file or screenshot showing the result of running your top-level test – 5
• Functional coverage points plus code coverage and functional coverage reports – 10
• Overall completeness of verification, including some form of checking – 20
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