程序代写 CSU11021 – Introduction to Computing I

5.1 (Binary) Arithmetic
CSU11021 – Introduction to Computing I
Dr | School of Computer Science and Statistics
© / Trinity College Dublin 2015 – 2021

Decimal numeral system
We are most familiar with the decimal numeral system 10 symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
What happens if I want to represent this number of apples?
Counting the apples … 1, 2, 3, 4, 5, 6, 7, 8, 9 … we’ve run out of digits!
… but, if we write down a digit represent the count of 10s of apples
… followed by another digit representing the count of single (unit) apples
… then we can express the number of apples as 12 or (1 x 101) + (2 x 100) This method of expressing a value is known as a “positional”
because the position of a digit corresponds to the magnitude of its contribution to the overall quantity (number of 1000s of apples, number of 100s of apples, number of 10s of apples and number of single apples)
with the rightmost digit (the least significant digit) corresponding to 100 (=1) the next rightmost digit corresponding to 101, then 102, then 103 etc.
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Binary numeral system
Binary is another positional numeral system 2 symbols: 0, 1
What happens if we want to represent the same number of apples in binary?
Counting the apples … 0, 1 … we’ve run out of digits!
… but, if we write down a digit represent the count of 2s of apples
… followed by another digit representing the count of single (unit) apples
… we can count up to 11 apples
… so we need another digit, this time representing the count of 4s of apples (4=22) … now we can represent 111 apples
Still not enough digits!
If we follow the same pattern with one more digit, we can represent the number of apples as 1100 or (1 x 23) + (1 x 22) + (0 x 21) + (0 x 20)
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Binary Arithmetic – Addition
Binary Decimal equivalent
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What happens if we run out of digits?
Adding two numbers each stored in 1 byte (8 bits) may produce a 9-bit result
Decimal equivalent
Added 15610 + 16710 and expected to get 32310
8-bit result was 010000112 or 6710
Largest number we can represent in 8-bits is 255
The “missing” or “left-over” 1 is called a carry (or carry-out)
8-bits just for illustration here. Our ARM processor has 32-bit registers and performs 32-bit arithmetic so we get a carry- out if our result requires 33 bits.
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Condition Code Flags
Some instructions can optionally update the Condition Code Flags to provide information about the result of the execution of the instruction
e.g. whether the result of an addition was zero, or negative or whether a carry occurred
Current Program Status Register (CPSR)
31 30 29 28 0
Condition Code Flags
N – Negative
V – oVerflow
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Condition Code Flags
The Condition Code Flags (N, Z, C, V) can be optionally updated to reflect the result of an instruction
S-bit in a machine code instruction is used to tell the processor whether the Condition Code Flags should be updated, based on the result
e.g. want to update Condition Code Flags during an ADD instruction Condition Code Flags only updated if (machine code) S-bit (bit 20) is 1
ADD instruction machine code
31 21 20 19 16 15 12 11 4 3 0
In assembly language, we cause the Condition Code Flags to be updated by appending “S” to the instruction mnemonic (e.g. ADDS, SUBS, MOVS)
11100000100
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Carry Flag
LDR R0, =0xC0000000
LDR R1, =0x70000000
ADDS R0, R0, R1
stop B stop
ADDS causes the Condition Code Flags to be updated
REMEMBER: 32-bit arithmetic!! Expected result?
Does the result fit in 32-bits?
Will the carry flag be set?
Examine by running the program …
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CMP Instruction and the Condition Code Flags
CMP (CoMPare) instruction performs a subtraction without storing the result of the subtraction
Processor remembers the properties of the CMP result by updating the Condition Code Flags
Allows us to determine equality (=) or inequality (< ≤ ≥ >) Don’t care about absolute value of result
(i.e. don’t care by how much x is greater than y, only whether it is or not.) CMP always sets the Condition Code Flags (so no need for CMPS)
CMP R2, #0 @ subtract 0 from R2, ignoring result but
BEQ – Branch if EQual
(or more precisely branch if the Zero flag is set)
@ updating the CC flags
BEQ EndWh @ if the result was zero then branch to EndWh
… … @ otherwise (if result was not zero) then keep
@ going (with sequential instruction path)
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5.2 Negative numbers and 2s complement
CSU11021 – Introduction to Computing I
Dr | School of Computer Science and Statistics
© / Trinity College Dublin 2015 – 2021

Negative Numbers
What does the binary value stored in memory at address 0xA0000138 represent?
Interpretation!
How can we represent signed values, and negative values such as -1710 in particular, in memory?
How can we tell whether any given value in memory represents an unsigned value, a signed value, an ASCII character or something else?
(we can’t tell … as programmers we have to know)
0xA0000142
0xA0000141
0xA0000140
0xA0000139
0xA0000138
0xA0000137
0xA0000136
0xA0000135
0xA0000134
8 bits = 1 byte
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Sign-Magnitude (this is not how we usually represent negative numbers!!)
Represent signed values in the range [ (-231-1) … (+231-1) ]
Two representations of zero (+0 and -0)
Would need special way to handle signed arithmetic (i.e. a separate circuit) Remember: interpretation! (is it -8 or 2,147,483,656?)
0000000000000000000000000001000
0000000000000000000000000001000
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Modulo Arithmetic
A 12-hour clock is an example of modulo-12 arithmetic
If we add 4 hours to 10 o’clock we get 2 o’clock
If we subtract 4 from 2 o’clock we get 10 o’clock (not -2 o’clock!)
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2’s Complement
Can represent 16 values with a 4-bit number system (24 = 16)
Ignoring carries from 4-bit binary addition gives us modulo-16 arithmetic (handy)
(15 + 1) mod 16 = 0 and -1 + 1 = 0
(14 + 2) mod 16 = 0 and -2 + 2 = 0
(14 + 4) mod 16 = 2 and -2 +4 = 2
1110! 1101! 13!
1100! 12! 11!
0000! 0001!
4! 0100! 5!
1000! 0111!
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2’s Complement
1111! 0000!
1-42!! 12! 11!
1011! 1-51!! 1010!
+5! 0101! 0110!
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2’s Complement Examples
Represent -9710 using 2’s complement
9710 = 011000012 Inverting gives 100111102 Adding 1 gives 100111112
Interpreted as a 2’s complement signed integer 100111112 = -9710
Interpreted as an unsigned integer 1001 11112 = 15910
Again, 8-bit values for illustration only here! In practice, we’ll be working with 32-bit values
(159 + 97) mod 256 = 0
Correct interpretation is the responsibility of the programmer, not the CPU CPU does not “know” whether a value 100111112 in R0 is -9710 or 15910
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2’s Complement Examples
Adding 011000012 (+9710) and 100111112 (−9710)
Ignoring the carry bit gives us the correct result of 0
Changing sign of 1001 11112 (−9710)
Invert bits and add 1 again Inverting gives 011000002 Adding 1 gives 011000012 (+9710)
Decimal equivalent
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Changing Sign in Assembly Language
Write an Assembly Language program to change the sign of the value stored in R0
Sign of a 2’s Complement value can be changed by inverting the value (bits) and adding 1
LDR r0, =7 ; value = 7 (simple test value)
MVN r0, r0 ; value = NOT value (invert bits)
ADD r0, r0, #1 ; value = value + 1 (add 1)
ARM Instruction Set provides a single instruction for this purpose
LDR r0, =7 ; value = 7 (simple test value)
NEG r0, r0 ; value = -value
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Subtraction
Decimal equivalent
A + TwosComplement(B)
Decimal equivalent
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5.3 oVerflow
CSU11021 – Introduction to Computing I
Dr | School of Computer Science and Statistics
© / Trinity College Dublin 2015 – 2021

2’s Complement Example
Decimal equivalent
Result is 100011102 (14210, or -11410)
If we were interpreting the two added values and the result as signed
integers, we got an incorrect result:
We added two +ve numbers and obtained a –ve result
With 8-bits, the highest +ve integer we can represent is +127 100011102 (-11410)
The result is outside the range of the signed number system
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If the result of an addition or subtraction gives a result that is outside the range of the signed number system, then an oVerflow has occurred
The processor sets the oVerflow Condition Code Flag after performing an arithmetic operation to indicate whether an overflow has occurred
Current Program Status Register
31 30 29 28 0
Condition Code Flags
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Carry and oVerflow – Interpretation!
Carry and oVerflow flags always set by the processor regardless of our signed or unsigned interpretation of stored values
Processor does not “know” what our interpretation is
e.g. we could interpret the binary value 100011102 as either 14210 (unsigned) or -11410 (signed)
(we could also interpret it as the code for “Ä” or as the colour blue)
The C and V flags are set by the processor and it is our responsibility to choose:
whether to interpret C or V (are we interpreting the values as unsigned or signed?) how to interpret C or V
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oVerflow Rules
Addition rule (r = a + b)
V = 1 if MSB(a) = MSB(b) and
MSB(r) ≠ MSB(a)
i.e. oVerflow accurs for addition if the operands have the same sign and the result has a different sign
Subtraction rule (r = a – b)
V = 1 if MSB(a) ≠ MSB(b) and
MSB(r) ≠ MSB(a)
i.e. oVerflow occurs for subtraction if the operands have different signs and the sign of the result is different from the sign of the first operand
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Carry and oVerflow Example
Decimal equivalent
Signed interpretation: (+112) + (-80) = +32 Unsigned interpretation: 112 + 176 = 288
By examining the V flag (V = 0), we know that if were interpreting the values as signed integers, the result is correct
If we were interpreting the values as 8-bit unsigned values, C = 1 tells us that the result was too large to fit in 8-bits
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Carry and oVerflow Example
Decimal equivalent
Signed: (-80) + (-80) = -160 Unsigned: 176 + 176 = 352
By examining the V flag (V = 1), we know that if were interpreting the values as signed integers, the result is outside the range of the signed number system
If we were interpreting the values as 8-bit unsigned values, C = 1 tells us that the result was too large to fit in 8-bits
Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015 – 2021

Condition Code Flags – Recap
Current Program Status Register (CPSR)
31 30 29 28 0
Many instructions can optionally cause the processor to update the Condition Code Flags (N, Z, V, and C) to reflect certain properties of the result of an operation
Append “S” to instruction in assembly language (e.g. ADDS) Set S-bit in machine code instruction
N flag set to 1 if result is Negative (i.e. if MSB is 1)
Z flag is set to 1 if result is Zero (i.e. all bits are 0)
C flag set if Carry occurs (addition) or borrow does not occur (subtraction) V flag set if oVerflow occurs for addition or subtraction
Remember: Processor updates NZVC regardless of our interpretation of values as signed or unsigned
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5.4 Condition Code Flag examples
CSU11021 – Introduction to Computing I
Dr | School of Computer Science and Statistics
© / Trinity College Dublin 2015 – 2021

LDR R0, =0xC0000000
LDR R1, =0x70000000
ADDS R0, R0, R1
Is the Carry flag set?
Is the oVerflow flag set? Is the Zero flag set?
Is the Negative flag set?
Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015 – 2021

LDR R0, =0xC0000000
LDR R1, =0x40000000
ADDS R0, R0, R1
Is the Carry flag set?
Is the oVerflow flag set? Is the Zero flag set?
Is the Negative flag set?
Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015 – 2021

LDR R0, =0xC0000000
LDR R1, =0x90000000
ADDS R0, R0, R1
Is the Carry flag set?
Is the oVerflow flag set? Is the Negative flag set?
Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015 – 2021

LDR R0, =0xC0000000
LDR R1, =0x30000000
ADD R0, R0, R1
Is the Carry flag set?
Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015 – 2021

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