程序代写 CSU11022 – Introduction to Computing II

1.1 – Memory and Addressing Modes
CSU11022 – Introduction to Computing II
Dr / School of Computer Science and Statistics

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Recap: LDR and STR

LDR and STR Reviewed
How many memory accesses are required to compute
total = total + (a ⨉ b)
where total, a and b are stored in memory at the addresses contained in R0, R1 and R2 respectively?
0x20001010
0x2000100C
0x20001008
0x20001004
0x20001000
ARM Cortex-M4 CPU core
Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022

LDR and STR Reviewed
How many memory accesses are required to compute total = total + (a ⨉ b), where total, a
and b are stored in memory at the addresses contained in R0, R1 and R2 respectively?
0x20001010
0x2000100C
0x20001008
0x20001004
0x20001000
LDR R5, [R1] @ Load a
LDR R6, [R2] @ Load b
MUL R5, R6, R5 @ tmp = a * b
LDR R4, [R0] @ Load total
ADD R4, R4, R5 @ total = total + (tmp)
ARM Cortex-M4 CPU core
STR R4, [R0] @ Store total back to memory
Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022
LDR R5, [R1]
LDR R6, [R2] LDR R4, [R0]
STR R4, [R0]

Recap: Upper Case String Example
Design and write an assembly language program to convert a string stored in memory to UPPER CASE
While: @
LDRB R2, [R1] @ while ((ch = byte[address]) != 0)
CMP R2,#0 @
BEQ EndWhile @ {
CMP R2, #’a’ @ if (ch >= ‘a’ && ch <= 'z') BLO EndIfLwr @ { CMP R2,#'z' @ BHI EndIfLwr @ SUB R2, R2, #0x20 @ ch = ch - 0x20; STRB R2, [R1] @ byte[address] = ch; EndIfLwr: @ } ADD R1, R1, #1 @ address = address + 1; B While @ } Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Recap: Sum Example Design and write an assembly language program that will calculate the sum of 10 word-size values stored in memory, beginning at the address in R1. Store the sum in R0. MOV R0, #0 @ sum = 0; MOV R2, #0 @ i = 0; CMP R2, #10 @ while (i < 10) BHS EndWhile @ { LDR R3, [R1] @ value = word[address]; ADD R0, R0, R3 @ sum = sum + value; ADD R1, R1, #4 @ address = address + 4; ADD R2, R2, #1 @ i = i + 1; B While @ } Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Addressing Modes: Immediate Offset Addressing Modes 0x20001010 0x2000100C 0x20001008 0x20001004 0x20001000 “points to” The syntax [R1] is just one of many ways that we can specify the address of the memory location that we want to access using LDR or STR Remember: [R1] tells the processor to access the value in memory at the address contained in register R1. (We can say that R1 “points to” a location in memory.) The syntax [R1] is an Addressing Mode [R1] is an abbreviated form of [R1, #0] (the #0 is implied if omitted) The address of the memory location accessed by LDR or STR is called the Effective Address (EA) R1 0x20001008 Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Immediate Offset Addressing Addressing Mode Syntax Operation Example [Rn, #offset] EA = Rn + offset LDR R0, [R1, #4] EA = Rn + #0 (#0 is assumed) LDR R0, [R1] Effective Address is calculated by adding offset to the address in the base register Rn (note: offset may be negative) The value in the base register Rn does not change Example: load three consecutive word-size values from memory into registers R4, R5 and R6, beginning at the address contained in R0 LDR R4, [R0] @ R4 = word[R0 + 0] (default = 0) LDR R5, [R0, #4] @ R5 = word[R0 + 4] LDR R6, [R0, #8] @ R6 = word[R0 + 8] Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Addressing Modes: Register Offset Register Offset Addressing Addressing Mode Syntax Operation Example EA = Rn + Rm LDR R0, [R1, R2] Effective Address is calculated by adding the offset in Rm to the address in the base register Rn The values in the base register Rn and offset register Rm do not change Example: load three consecutive word values from memory into registers R1, R2 and R3 beginning at the address in R0 LDR R4, =0 @ Initialise offset register = 0 LDR R1, [R0, R4] @ r1 = word[r0 + r4] ADD R4, R4, #4 @ r4 = r4 + 4 LDR R2, [R0, R4] @ r2 = word[r0 + r4] ADD R4, R4, #4 @ r4 = r4 + 4 LDR R3, [R0, R4] @ r3 = word[r0 + r4] Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Register Offset Addressing 0x20001010 0x2000100C 0x20001008 0x20001004 0x20001000 Loading 1st Word Loading 2nd Word Loading 3rd Word R0 0x20001004 + R4 0 0x20001010 0x2000100C 0x20001008 0x20001004 0x20001000 R0 0x20001004 + R4 4 0x20001010 0x2000100C 0x20001008 0x20001004 0x20001000 R0 0x20001004 + R4 8 Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 1.2 – Memory and Addressing Modes (continued) CSU11022 – Introduction to Computing II Dr / School of Computer Science and Statistics UPPER CASE (using Register Offset Addressing) LDR R2, =0 @ index = 0 LDRB R4, [R1, R2] @ CMP R4, #0 @ while ( (char = byte[address + index]) != 0 ) BEQ eWhUpr @ { CMP R4, #'a' @ if (char >= ‘a’
BLO eIfLwr @ &&
CMP R4, #’z’ @ char <= 'z') BHI eIfLwr @{ BIC R4, #0x00000020 @ char = char AND NOT 0x00000020 STRB R4, [R1, R2] @ byte[address + index] = char eIfLwr: @ } ADD R2, R2, #1 @ index = index + 1 B whUpr @ } eWhUpr: @ Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Sum (using Register Offset Addressing) Design and write an assembly language program that will calculate the sum of 10 word-size values stored in memory beginning at the address in R1 LDR R0, =0 @ sum = 0 LDR R4, =0 @ count = 0 LDR R5, =0 @ offset = 0 CMP R4, #10 @ while (count < 10) BHS eWhSum @ { LDR R6, [R1, R5] @ num = word[address + offset] ADD R0, R0, R6 @ sum = sum + num ADD R5, R5, #4 @ offset = offset + 4 ADD R4, R4, #1 @ count = count + 1 B whSum @ } eWhSum: @ Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Addressing Modes: Scaled Register Offset Scaled Register Offset Addressing Addressing Mode Syntax Operation Example [Rn, Rm, LSL #shift] EA = Rn + (Rm x 2shift) LDR R0, [R1, R2, LSL #2] Effective Address is calculated by adding offset in Rm, shifted left by shift bits, to the address in the base register Rn The values in the base register Rn and offset register Rm are not changed Example: load three consecutive word-size values from memory into registers R1, R2 and R3 beginning at the address in R0 LDR R4, =0 @ Initialise index register = 0 LDR R1, [R0, R4, LSL #2] @ R1 = word[r0 + r4 * 4] ADD R4, R4, #1 @ R4 = r4 + 1 LDR R2, [R0, R4, LSL #2] @ R2 = word[r0 + r4 * 4] ADD R4, r4, #1 @ R4 = r4 + 1 LDR R3, [R0, R4, LSL #2] @ R3 = word[r0 + r4 * 4] Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Sum (using Scaled Register Offset Addressing) Re-write our program to calculate the sum of 10 word-size values stored in memory, this time using scaled register offset addressing Allows count to be used for offset!! LDR R0, =0 @ sum = 0 LDR R4, =0 @ count = 0 CMP R4, #10 @ while (count < 10) BHS eWhSum @ { LDR R6, [R1, R4, LSL #2] @ num = word[address + (count * 4)] ADD R0, R0, R6 @ sum = sum + num ADD R4, R4, #1 @ count = count + 1 B whSum @ } eWhSum: @ Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Addressing Modes: Pre- and Post-Indexed Addressing Pre- and Post-Indexed Addressing Many programs iterate sequentially through memory (examples?) Often manifested as an LDR/STR, followed by an ADD LDR R4, [R1] ; load word ADD R1, R1, #4 ; increment base address register R1 ARM architecture provides a set of addressing modes that incorporate the increment/decrement into the execution of the LDR/STR instruction Pre-Indexed Addressing Post-Indexed Addressing 1. Increment / Decrement base address register (Rn) 2. Compute Effective Address 1. Compute Effective Address 2. Increment / Decrement base address register (Rn) Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Post-Indexed Addressing Modes LDR R4, [R1] ADD R1, R1, #4 Immediate Offset Addressing LDR R4, [R1], #4 Immediate Post-Indexed Addressing Syntax: post-indexed addressing modes place the value to be added to the base register Rn after the [ ] Behaviour: (i) the LDR/STR is performed first using the original base register value, (ii) the base register is updated by applying the post- index operation Modes: Immediate Post-Indexed, Register Post-Indexed, Scaled Register Post-Indexed (LSL #shift) Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Pre-Indexed Addressing Modes ADD R1, R1, #4 LDR R4, [R1] Immediate Offset Addressing LDR R4, [R1, #4]! Immediate Pre-Indexed Addressing Syntax: pre-indexed addressing modes place the value to be added to the base register Rn inside the [ ] An exclamation mark ! after the [ ] distinguishes pre-indexed addressing from immediate offset addressing (e.g. [R1, #4]), which doesn’t modify R1 Behaviour: (i) the base register is updated by applying the pre-index operation, (ii) the LDR/STR is performed using the updated base register value Modes: Immediate Pre-Indexed, Register Pre-Indexed, Scaled Register Pre- Indexed (LSL #shift) Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 UPPER CASE (using Immediate Post-Indexed Addressing) LDRB R4, [R1], #1 @ char = byte[address++] CMP R4, #0 @ while ( char != 0 ) BEQ eWhUpr @ { CMP R4, #'a' @ if (char >= ‘a’
BLO eIfLwr @ &&
CMP R4, #’z’ @ char <= 'z') BHI eIfLwr @{ BIC R4, #0x00000020 @ char = char AND NOT 0x00000020 STRB R4, [R1, #-1] @ byte[address - 1] = char eIfLwr: @ } B whUpr @ } eWhUpr: @ Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Sum (using Immediate Post-Indexed Addressing) LDR R0, =0 @ sum = 0 LDR R4, =0 @ count = 0 CMP R4, #10 @ while (count < 10) BHS eWhSum @ { LDR R6, [R1], #4 @ num = word[address]; address = address + 4; ADD R0, R0, R6 @ sum = sum + num ADD R4, R4, #1 @ count = count + 1 B whSum @ } eWhSum: @ Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 1.3 – Arrays CSU11022 – Introduction to Computing II Dr / School of Computer Science and Statistics Single-Dimensional Arrays Nothing new here ... you have already been using arrays! Array – an ordered collection of homogeneous elements stored sequentially in memory e.g. integers, ASCII characters “Homogeneous elements”? (for us, at least with respect to size) “Dimension” number of elements in array 0x20000030 0x2000002C 0x20000028 0x20000024 0x20000020 0x2000001C 0x20000018 0x20000014 0x20000010 0x2000000C 0x20000008 0x20000004 0x20000000 memory index 5 4 3 2 1 0 32 bits = 4 bytes = 1 word Trinity College Dublin, The University of Dublin © / Trinity College Dublin 2015-2022 Accessing (loading/storing) Array Elements Step 1: translate array index into byte offset from start address of array in memory = ×
Step 2: add byte offset to array base address to access element