Of course, the hardware doesn¡¯t really execute MIPS assembly language code.
The hardware can only store bits, and so the instructions it executes must be expressed in a suitable binary format.
We call the language made up of those instructions the machine language.
Different families of processors typically support different machine languages.
In the beginning, all programming was done in machine language… very ugly… Assembly languages were created to make the programming process more human-centric. Assembly language code is translated into machine language by an assembler.
Alas, there is no universal assembly language. In practice, assembly languages are tightly coupled with the underlying machine language and hardware.
Machine Language MIPS ML 1
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Assembly provides convenient symbolic representation
– much easier than writing down numbers
– e.g., destination first
Machine language is the underlying reality
– e.g., destination is no longer first
Assembly can provide ‘pseudoinstructions’
– e.g., ¡°move $t0, $t1¡± exists only as an extension to assembly
– would be translated to ¡°add $t0,$t1,$zero¡± by the assembler
When considering performance you should count real instructions
Assembly Language vs. Machine Language MIPS ML 2
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Examining the (basic) MIPS assembly instructions, we can easily identify three fundamentally different categories, according to the parameters they take:
– instructions that take 3 registers
add $s0, $s1, $s2 or $t1, $t0, $t1
– instructions that take 2 registers and an immediate (offset, number, address, etc.)
addi $t7, $s5, 42
lw $s3, 12($t4)
beq $t1, $t3, Label01
– instructions that take an immediate
j Label01
Classifying the Assembly Instructions MIPS ML 3
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Simple instructions, all 32 bits wide
Very structured, no unnecessary baggage
Only three instruction formats with strictly-defined fields:
R
I J
R-format: I-format J-format:
op
rs
rt
rd
shamt
funct
op
rs
rt
16-bit immediate
op
26-bit immediate
basic arithmetical-logical instructions load/store/conditional branch instructions jump/unconditional branch instructions
Overview of MIPS Machine Language MIPS ML 4
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In MIPS32 Release 2, there are over 200 basic MIPS machine instructions.
In order to specify that many different instructions, we could use a field of 7 or more bits in every machine instruction.
But MIPS machine language uses a 6-bit opcode field and a variety of special cases. For R-format instructions, the opcode field is set to 000000, and the last 6 bits specify
exactly which arithmetic/logical instruction is to be performed.
R
I J
op
rs
rt
rd
shamt
funct
op
rs
rt
16-bit immediate
op
26-bit immediate
Overview of MIPS Machine Language MIPS ML 5
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Instructions, like registers and words of data, are also 32 bits long Example: add $t1, $s1, $s2
registers have numbers, $t1 = 9, $s1 = 17, $s2 =18
Machine language basic arithmetic/logic instruction format:
op rs rt rd shamt funct
Can you guess what the field names stand for?
000000
10001
10010
01001
00000
100000
op operation code (opcode)
rs 1st source register
rt 2nd source register
rd destination register shamt shift amount
funct opcode variant selector
Arithmetic/Logical Instructions MIPS ML 6
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Note how the assembly instruction maps into the machine representation:
add $t1, $s1, $s2
000000
10001
10010
01001
00000
100000
op rs rt rd shamt funct
The three register fields are each 5 bits wide. Why?
For arithmetic-logical instructions, both the op field and the funct field are used to specify the particular operation that is to be performed.
If you view memory contents, this would appear as 0x02324820.
Mapping Assembly to Machine Language MIPS ML 7
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Consider the load-word and store-word instructions:
– what would the regularity principle have us do?
– new principle: Good design demands a compromise
We need a different type of machine language instruction format for these:
– I-type for data transfer instructions
– other format was R-type for register
Example: lw $t0, 32($s2)
op rs rt 16-bit number
Where’s the compromise?
100011
10010
01001
0000 0000 0010 0000
Load Instructions MIPS ML 8
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Consider the jump instruction: j Label01
We need a different type of machine language instruction format for this as well.
Example: j exit # assume exit is a statement label
000010
26-bit offset depending on value of exit
Jump Instructions MIPS ML 9
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What will be involved in executing a machine language instruction? Consider an I-type instruction, say a lw instruction:
op
rs
rt
16-bit immediate
I
The opcode bits must be analyzed to determine that the instruction is lw.
The contents of $rs must be fetched to the ALU and added to the immediate field to compute the appropriate address.
The contents at that address must be fetched from memory and written to register $rt.
Anticipating Execution MIPS ML 10
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