EEE230 Introduction to Pipelining Practice problems
Use this segment of code to answer these questions.
addi $t1, $0, 0 sub $t2, $t2, $t2 or $t3, $t3, $t3 add $t4, $t4, $t4 ori $t1, $0, 0
1. Assuming negligible delays except: memory (250ps), ALU and adders (200ps), register file access (100ps). Instruction and data memory and register file read and write are all counted separately.
How long does the code take to execute on
a. The single cycle processor?
b. The pipelined processor?
2. Which instructions from the code above are in which stages during
a. The 3rd clock cycle
b. The 5th clock cycle
Answers
1.
a. 4500ps or 4.5ns
b. 2250ps or 2.25ns
2.
a. IF or, ID sub, EX addi
b. IF ori, ID add, EX or, MEM sub, WB addi