School of Electronic
and Electrical Engineering FACULTY OF ENGINEERING
ELEC5566M: FPGA Design for System on Chip
Mini-Project
State machine based digital lock
This assignment has a weighting of 50% (25% Report, 25% Demonstration/Presentation)
Assignment issued on 18th March 2020 Deadline is Wednesday 6th May 2020 at 11am
Report Submission is via TurnitIn
Page Limit of 5 pages (Appendix is excluded from page limit)
Code and Presentation Submission is via Minerva
Prof Steven Freear Dr David Cowell Mr Thomas Carpenter
ELEC5566M: FPGA Design for System on Chip – Mini-Project Mini-Project: State machine based digital lock
Mini-Project: State machine based digital lock
Project Brief
The aim of the mini-project is to program the DE1-SoC development board to create a digital lock. This will allow you
to demonstrate ALL the skills you have learnt in this module. The exact implementation of the project brief is up to your digression. Every solution will be distinct and individual.
You will be working individually on the solution and will create a report outlining the details of the system and its design, with evidence of as much testing, both simulation and hardware, as is required to verify your design. The report will be assessed according to the rubric used for your previous assignments in ELEC5566M.
We do appreciate that your access to physical test equipment will be limited during the next few weeks. As such, please describe in your report a testing plan for any tests that you have been unable to perform that require equipment such as oscilloscopes or signal generators etc.
Plan your time giving consideration to your other commitments and try to minimize the effects of the current unpredictable situation.
The project will be marked according to the following criteria:
Minimum requirements
• The system should use the button inputs, KEY[3:0], and lock or unlock based on the user pressing a sequence of four button presses as a PIN code.
• When unlocked the user should be able to lock the system by entering an identical sequence of button presses twice. If the second button sequence does not match the first, the system should remain unlocked and display an error message.
• When locked, the user should be able to unlock by entering the original sequence of button presses that locked the device. If an attempt to unlock the system using an incorrect sequence of button presses is made, the system should remain locked and an error message displayed.
• The system should use the 7-segment LEDs as a display. When the system is locked, “LOCKED” or similar should be displayed on the 7 segment LEDs. When the system is open, “OPEN” or similar should be displayed on the 7 segment LEDs.
How to get better marks:
To get better marks, your project should make use of the following:
• Switch debugging.
• Advanced user interfaces/displays.
• Timeouts when the user stops entering keys.
• Longer button locking sequences than four button presses
To get even better marks, you should be:
• Developing fully parameterised and generalised custom IP blocks.
• Building complex and suitable hierarchical designs.
2
Mini-Project Assessment
ELEC5566M: FPGA Design for System on Chip – Mini-Project Mini-Project Assessment
This mini-project is assessed forming a total module weighting of 50%.
This is split as 25% Technical Report with code submission and 25% Presentation including Demo.
You must submit your report via Turnitin and Code and Presentation via Minerva before the deadline. A 5% per day/partial day penalty will be subtracted from your score for late submission.
If you encounter technical difficulties during submission, you must email your report plus code and presentation as a zipped file to d.m.j.cowell@leeds.ac.uk before the deadline and then submit the report, code and presentation without alteration through Minerva at the next available opportunity.
25% Technical Report (Turnitin Submission)
The report has a strict page limit of 5 technical pages. A 10% penalty will be incurred for each additional page over the limit. You should additionally include a cover page with the Report Title, your Name and SID. The cover page does not count towards the page limit.
You may additionally place supplementary diagrams and images in an Appendix, which will not count towards the page limit.
All of your source code MUST also be included, as neatly formatted text in the Appendix (which will not count towards the page limit). Screenshots/photos of code are not allowed and will not be marked!
Code Submission (Minerva Submission)
All of your project files including Verilog Files (.v) and test benches plus final Programming File (.sof), Quartus Project File (.qpf), Quartus Settings File (.qsf), and Map Report File (output_files/*.map.rpt), must be submitted to the separate code submission page on the Minerva. Please compress these files into a single zip format file.
25% Presentation including Demo (Minerva Submission)
You should create a 5 slide PowerPoint or Slideshow that highlights the key parts of the project along with what you have learned during the project work. The slides should include either photographs or a maximum of 2 minutes of video demonstration of your project. Photos or video need to clearly show the number label on your DE1- SoC board. You must have a working demonstration of your mini project.
Plagiarism
Sharing of code is not allowed.
The source of any IP cores or code structures from external sources (e.g. opencores.org, Quartus IP Catalog) must be clearly identified in the references section of your report and in comments within your code. You will not be awarded any marks for these parts of code, however you will not be penalised for using them so long as full reference to the source of the code is given.
Any external IP core or code found that has not been properly referenced, or any code shared between students, will be considered plagiarism and dealt with by the external University Plagiarism committee.
3