UCCD1133
Introduction to Computer Organisation and Architecture
Chapter 3
Basic Concept of Logic
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Chapter 3-6
Memory element and register
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Outline
• Delay flip-flops (DFF) • Registers
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Memory Elements
❑ Memory elements are the most primitive sequential circuits for storing a bit value.
❑ 2 types of memory elements Latch (clockless)
Flip-flop (clock based)
❑ Common types of flip-flop: Set-Reset flip-flop (SRFF).
JK flip-flop (JKFF).
Delay flip-flop (DFF)
Toggle flip-flop (TFF).
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Delay Flip-Flop (DFF)
❑ A flip-flop has edge sensitive behavior.
The output responds to the input data only during the active edge of the clock.
❑ Logic symbols of DFF:
Arrowhead: identifies an edge triggered device
Q Bubble indicates Q
❑
❑
The arrowhead pin: usually apply periodic signal – e.g. clock signal
OneFF->one clock pin
D
aset Q
Q areset
a falling edge Q_n detection
Q_n
(a) Positive-edge triggered DFF
(b) Negative-edge triggered DFF
Q Q_n
D
Q Q
(c) No aset and areset input
❑ Aset: output become 1; areset: output become 0. (asynchronous inputs – regardless of clock). ❑ When not used, aset and areset inputs no need to show. Its only logic symbol.
❑ But in actual hardware implementation, need to Connect them to values that de-activate them.
D
aset Q
Q areset
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Delay Flip-Flop (DFF)
❑ A DFF copies input value at D (from one cycle) to output Q (in the next cycle) when active clock edge occurs.
D flip-flop copies D to Q on the rising edge of the clock, and remembers its state at all other times
At other times, not copied.
(a) DFF logic symbol
clk D Q
DQ Q
Inputs
Output
Function
D
Q*
0 1
0 1
Copy Copy
x
(b) Function table
❑ 3 basic functionalities
To synchronise a signal to clock
(c) Timing diagram (rising/positive edge triggered)
– How? Copy value at D to Q only during the active edge of the clock. To delay a signal at D by one cycle.
– The value should appear at Q in the next cycle (relative to the time at D). To filter glitches that appears in a signal
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DFF with Enable
❑ However, the previous DFF cannot store or hold a signal value. ❑ To hold a value, need to add a hold function into DFF
→A DFF with enable
Inputs
Outputs
Function
Enable input E
D
Q*
0
d
Q
Hold
1
0
0
Copy
1
1
1
Copy
DQ
DQ
en
D en
clock
Q
(a) Creating a storage effect by adding a Hold function into a DFF
(b) DFF with enable
Function table for DFF with enable
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Example
❑ Example 1
Draw the output waveform of the positive-edge DFF given the input signals as below.
1 2 3 4 5 6 8 9 10 13
clock D aset areset
Solution 1
To draw the output waveform, the output is computed one cycle by one cycle during the clock transition of LOW-to-HIGH (positive edge).
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11 12
1 2 3 4 5 6 8 9 10 13
clock D aset areset Q
x
7
11 12
x
Depends on whether set or reset has the higher priority
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Example
❑ Example 2
Show how DFFs can be used to delay a signal by 3 clock cycles. Draw a timing
diagram to illustrate the delay. ❑ Solution 2
input
clk
areset
output
DQ areset
DQ areset
DQ areset
clk
areset input
output
5
0
1
2
3
4
x
3 cycles
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Registers
❑ Register consists of a set of N flip-flops with a common clock input. N is typically an integral power of 2
It is mainly build from D-type flip-flops
Data_in Data_out
D Qa areset
D Qb areset
clk
areset
(a) A four bit serial-in/serial out shift register
D Qc areset
❑ Registers can be replicated to build larger memory units. It is typically used as a fast temporary storage in a central processing unit (CPU).
❑ Each flip-flop can store one bit of information; therefore, the number of stages (flip-flops) in a register determines its storage capacity.
❑ A typical CPUs either store 32 or 64 bits in registers.
D Qd areset
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Register File
❑ A register file is a collection of registers.
Each of it is individually addressed.
By specifying the register number to be accessed, the register file can be read and written.
❑ Registers are grouped in array to form M x N register file M registers, each N-bit wide
E.g.4 x 32 dual-port
– Four 32-bit registers
❑ The interface of a register file should at least has: A clock signal (CLK)
An input to specify the register number (address) (A) An output read port (RD)
An input write port (WD)
A control bit(s) to enable/disable write operation (WE)
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