MIPS verilog汇编代写: ELEC373 Verilog Assignment 3

程序代写 CS代考 / MIPS汇编代写代考, Verilog代写

Assignment Outline

ELEC373 Verilog Assignment 3 (2017-2018) Synthesising the MIPS Processor

Assignment 3 is split into 2 parts, Part A and Part B. The objective of Part A is to get you familiar with the synthesised MIPS single cycle processor and to write some simple programs to control the processor. Part B requires you to extend the processor so that it will implement additional instructions.

MIPS_System

The Verilog Code for the MIPS single cycle implementation are available on VITAL. Download the ZIP file called MIPS_System and extract it into a suitable location. The synthesised MIPS processor starts executing a program from location 0x0000000. The program is loaded into the FPGA via a Memory Initialisation File, when you program the FPGA. In this design it is called “insts_data.mif”. If you examine this file using the Quartus software you’ll find that the data it contains is:

0x3C020000, 0x24420055, 0x3C03FFFF, 0x24632008, 0xAC620000, 0x080000005

If you disassemble this you’ll find that the first instruction corresponds to: lui $2, 0x0000

Using the MIPS Instruction Coding available from Vital, disassemble the other instructions to understand what the program does.

Memory Map

If you study the “Addr_Decoder.v” file you’ll find that the GPIO (General Purpose Input/Output) module is mapped from location 0xFFFF_2000. If you examine the “GPIO.v” file you’ll find the individual locations for the LEDs and switches on the DE2 board.

Program Execution

Compile and download the design, you should see that it switches on some of the red LEDs.

SignalTap Logic Analyser

You should configure the SignalTap logic analyser so that you can see the appropriate signals changing in the synthesised MIPS core when the MIPS CPU is running.

Assignment 3 Part A – 40%

  1. Modify the MIPS assembly language program so that the program displays the lowest 8 digits of your ID on the DE2 board 7 segment display.
  2. Show that your program functions correctly by taking a screen shot(s) of the SignalTap Logic analayser showing your program executing.
  3. In your report you should include your assembly language code and a screen dump of the SignalTap Logic analayser. Also include a photograph of the 7 segment displays showing your ID.

Assembling

You may find that hand-assembly is quite error prone and laborious. On Vital you’ll find a MIPS assembler (MARS 4.1) written in JAVA that will help you assemble your code. To get this to assemble code starting at location 0x0000000, select “Settings->Memory Configuration->Compact, Text at Address 0” that will ensure that any jumps have the correct memory location encoded.

Assignment 3 Part B – 60%

The MIPS deisgn presented in MIPS_System only implements a limited number of the MIPS instructions. For the R-Type instructions ADD, ADDU, SUB, SUBU, AND, OR and SLT are implemented. Your task is to modify the MIPS design so that it implements the additional instructions shown in Table 1 whilst still ensuring the existing instructions work correctly. Once you have modified your design you need to write a program to demonstrate that your hardware correctly implements the instructions. Your results should include print outs of the SignalTap logic analyser showing your program operating. Annotate the print out to explain what is happening. You should submit an electronic copy of your design and assembly language programs onto Vital. Your written report should explain what modifications you have made to the Verilog code and include the Verilog code you have developed. There is no need to include the Verilog code for the modules you haven’t modified. You should also include ASM/ASMD charts for your modified code. For

1

your report on instruction 3 you should include a block diagram showing the extra data pathways you have added.
Submission Deadline

Bench Inspection: Thursday 8th March 2018 Electronic copy: Friday 9th March 2018 @ 11:59pm

ID

201218886
201218991
201219101
201219109
201219153
201219251
201219267
201219337
201219342
201219565
201137136
201219577
201219587
201219603
201219719
201219751
201219762
201219763
201219829
201219871
201219878
201219906
201219938
201219994
201220008
201220024
201220009
201220002
201220041
201119429
201220057

Table 1 Instructions to implement

Level Instruction 1

UG nor UG xor UG nor UG xor UG nor UG xor UG nor UG xor UG nor UG xor UG nor UG xor UG Nor UG Xor UG Nor UG xor UG nor UG xor UG nor UG xor UG nor UG xor UG nor UG xor UG nor UG xor UG nor UG xor UG nor UG xor UG nor

Name

Dai, Yixing
Guan, Xingren
Jia, Yunwei
Jiang, Mengqi
Li, Chaoran
Lin, Zhijie
Liu, Juntong
Luo, Wei
Lyu, Tianqi
Tian, Jiawei
Tomadakis, Manolis Daniel Wan, Shun
Wang, Chongyun
Wang, Jiayi
Woo, Sukrit
Xia, Chenxi
Xiao, Jiahe
Xiao, Mingjun
Yan, Shihang
Yao, Ru
Ye, Chenxi
Yu, Haoyang
Zhang, Chenglu
Zhang, Xueqian
Zhang, Yichi
Zhang, Yuanlei
Zhang, Yuheng
Zhang, Yuxuan
Zhao, Liang
Zhao, Wenqi
Zhao, Zhe

Instruction 2

andi andi andi xori xori xori xori andi andi andi xori xori xori xori andi andi andi xori xori xori xori andi andi andi xori xori xori andi andi andi xori

Instruction 3

lb lbu lh lhu lb lbu lh lhu lb lbu lh lhu lb lbu lh lhu lb lbu lh lhu lb lbu lh lhu lb lbu lh lhu lb lbu lh

J.S. Smith 31/1/18

2

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