CAMOSUN COLLEGE E161:E.12
Department of Electronics 2020/10 Rev 3.2
ECET 161 Lab Exercise
Exercise 12
4-Bit Parallel Adder Design
Reference: Handouts
Lab preparation required: Design a 4-bit Parallel Adder with Carry. Produce a clear printout of the design.
Reference: Handouts
Lab preparation required: Design a 4-bit Parallel Adder with Carry. Produce a clear printout of the design.
REQUIRED:
• VHDL file and/or block diagram file for a 4-bit Parallel Adder with Carry.
• Construct the circuit and test using 8 bits of your dip switch and one digit of the seven segment display.
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• PROCEDURE:
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Construct a 4-bit Parallel Adder with Carry using a dip switch and one digit of the seven segment display as shown in Fig 1. This circuit will add two binary numbers from the dip switch and display the answer in HEX on one digit of the seven segment display. The LED will display the carry bit.
• Include the files from the 7-segment lab to make use of the decoder in your block diagram file.
• Produce the VHDL code for the full adder, create a block symbol, and add this to your block diagram file with all necessary connections.
Figure 1
Optional challenge:
For an additional challenge try the following: Try using an on board switch that will subtract the numbers when it is pushed. The unit will add when the button is not pushed. Only attempt this after the above lab and all other homework is complete.
Optional super challenge:
For an additional super challenge try the following: Multiplex the display so that the two input numbers are displayed and the answer is displayed. Use the following format:
Pin Plan for this Lab:
Screen shot of VHDL file for a Full Adder with Carry (fullVhdlAdder.vhd):
Screen shot of block diagram for a 4-bit Parallel Adder with Carry (adder4bit.bdf):
Screen shot of block diagram for top level (hex7segAdder.bdf):