COMPUTER ARCHITECTURE PROJECT 2020
The goal of this term-project is to implement a simulator of MIPS pipelined processors for handling data hazards. For the implementation, you can use C, C++, JAVA, or Python. However, your processor simulator should work as follows;
The execution command of your data hazard handler:
dhh_simulator
Input:
In an assembly language level
Only ADD, ADDI, OR, ORI, LW, SW are used Suppose that only register $1 ~ $8 are used
Example:
ADD $1, $2, $3 ORI $1, $2, 16 LW $2, 0($3) SW $4, 0($6)
Output:
In the output file, the following information must be contained. Control signal values at each clock cycle
IF/ID.registerRs
ID/EX.regWrite
MEM/WB.regWrite
IF/ID.registerRt
ID/EX.MemRead
ForwardA
IF/ID.registerRd
ID/EX.RegDst
ForwardB
ID/EX.registerRs
EX/MEM.registerRd
PCWrite
ID/EX.registerRt
EX/MEM.regWrite
IF/IDWrite
ID/EX.registerRd
MEM/WB.registerRd
ID/EXFlush
Example: cu_simulator test.in
Input: test.in
Output: test.out
ADD $1, $2, $3 ADDI $4, $1, 20
CC1
CC2
CC3
CC4
CC5
CC6
IF/ID.registerRs
0
2
1
0
0
0
IF/ID.registerRt
0
3
4
0
0
0
IF/ID.registerRd
0
1
0
0
0
0
ID/EX.registerRs
0
0
2
1
0
0
ID/EX.registerRt
0
0
3
4
0
0
ID/EX.registerRd
0
0
1
0
0
ID/EX.regWrite
0
0
1
1
0
0
ID/EX.memRead
0
0
0
0
0
0
ID/EX.RegDst
0
0
1
0
0
0
EX/MEM.registerRd
0
0
0
1
4
0
EX/MEM.regWrite
0
0
0
1
1
0
MEM/WB.registerRd
0
0
0
0
1
4
MEMWB.regWrite
0
0
0
0
1
1
ForwardA
00
00
00
10
00
00
ForwardB
00
00
00
00
00
00
PCWrite
1
1
1
1
1
1
IF/IDWrite
1
1
1
1
1
1
ID/EXFlush
0
0
0
0
0
0
Considerations
You MUST consider pipeline stalls caused by load-use data hazards When the signal value is invalid, then write 0
You can change the format of output files
Term-project schedule and submission
Deadline: 12/19, 23:59 (through an e-class system)
For a delayed submission, you will lose 0.1 * your original project score per each
delayed day
Submission file:
The compressed file should contain
The source code of your simulator with detailed comments Documentation (the most important thing!)
It must include all about your implementation
Test input files and outputs which you used in this project
The test input files are not given. You should make the test files, by yourself, which can examine all the token patterns.
If you have any question, please send an e-mail to hskimhello@cau.ac.kr