Computer Systems Week 2 (part 2)
Instructions, Assembly Language, and Machine Code
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Lecture Objectives
To develop fundmental understading of computer architecture & organization, instruction sets and
assembly language programming.
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Lecture Outline
u The von Neumann Architecture uCPU Cycles and Instruction Pipelining u The Harvard Architecture
uCase Study – MIPS R4000
nStructure
nKey Features nAssembly Languages nInstruction Sets nMIPS Instruction Types
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Review – The von Neumann Architecture (1/4)
Image Source: https://www.mpoweruk.com/computer_architecture.htm
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The von Neumann Architecture (2/4)
uThe Central Processing Unit (CPU) uThe CPU consists of:
nControl Unit
nArithmetic and Logical Unit (ALU)
n Registers
uProgram Counter – Address of the Next Instruction
uInstruction Register – Instruction currently being executed or decoded uAddress Register – Either stores the memory address from which data will be fetched, or the address to which data will be sent and stored
uAccumulator (Register) – short-term, intermediate storage of arithmetic and logic data computations
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The von Neumann Architecture (3/4)
uSystem Bus
nControl Bus – carries commands
from the CPU and returns status
signals from the devices
nData Bus – carries the actual data
being processed
nAddress Bus – carries memory
addresses from the processor to other components
uMemory (RAM) uInput / Output Units
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The von Neumann Architecture (4/4)
uClock Cycle
nA signal that oscillates between
high and low – used to synchronise
(coordinate) actions.
nThe number of cycles that a CPU
uses per second is used to
determine its speed.
lThis is measured in megahertz
(MHz) and gigahertz (GHz)
nThe rate of the Fetch/Execute Cycle is determined by the computer’s clock.
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One Cycle per Clock Tick
uA computer with a 1 GHz clock has one billionth of a
second—one nanosecond—between clock ticks to run the
Fetch/Execute Cycle.
n In that amount of time, light travels about one foot (~30 cm). uModern computers try to start an instruction on each clock
tick.
uThey pass off completing the instruction to other circuitry. This process is called pipelining and frees the fetch unit to start the next instruction before the last one is done.
n It is not quite true that 1,000 instructions are executed in 1,000 ticks
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Schematic Fetch/Execute Cycle (Pipelining)
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The von Neumann Architecture – Example
Demo:
http://peterhigginson.co.uk/LMC/
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The Harvard Architecture
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Comparison – von Neumann vs Harvard
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Case Study – MIPS R4000
uSimilar to von Neumann but separate interfaces to instructions and data.
lModified Harvard architecture
https://en.wikipedia.org/wiki/R4000
https://en.wikipedia.org/wiki/SGI_Onyx
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Case Study – MIPS R4000
uFirst 64-bit architecture
uIntegrated caches (on-chip, off-chip secondary cache) uIntegrated Floating Point Unit (FPU)
uImplemented in 1991 nDeep pipeline
n1.4M transistors
nInitially 100 MHz (>50 MIPs)
uSimple, well-behaved programming model
uCompact set of instructions with regular format (MIPS III)
u“Easy” to translate from high-level code to machine language
Comparison: http://www.alexvoica.com/wp- content/uploads/2015/09/great-mips-chips- past_f.png
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Typical MIPS Pipeline
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MIPS R4000 Pipeline
u8 stage pipeline (super-pipelined)
uExtend IF and MEM stages to account for cache overheads
nSplit int “First” and “Second” stages followed by a “Tag Check” for misses
nThe IF tag check is done in the RF stage
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MIPS R4000 Pipeline Stages
1) IF : First half of instruction fetch; PC selection actually happens here, together with initiation of instruction cache access
2) IS : Second half of instruction fetch, complete instruction cache access.
3) RF : Instruction decode and register fetch, hazard checking, and also instruction cache hit detection
4) EX : Execution, which includes effective address calculation, ALU operation, and branch target completion of data cache access
5) DF : Data fetch, first half of data cache access
6) DS : Second half of data fetch, completion of data cache access
7) TC : Tag check, determine whether the data cache access hit
8) WB : Write back for loads and register-register operations
Source:
https://www.cs.umd.edu/~meesh/cmsc411/website/p roj01/MIPS4000/Intro.htm
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MIPS R4000 Pipeline Stages
Source:
http://www.cabrillo.edu/~shodges/cs24/files/MIPS_R 0400_Users_Manual.pdf
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MIPS R4000 – Key Features
uProgram counter, instruction register, control unit, FPU.
u32 x 32-bit / 64-bit registers, denoted $0-$31 (or r0-r31)
uCPU registers can be either 32 bits or 64 bits wide, depending on the R4000 processor mode of operation.
u$0 (r0) always stores 000…000
u$31 (r31) is is the link register used by Jump and Link
instructions. It should not be used by other instructions.
uArithmetic and Logic unit
nTakes input from up to two registers
nSends output to registers only
nOne exception: also used to calculate memory addresses
Note: In the remainder of lecture, we will talk about 32-bit registers only and denote them using $ notation.
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Assembly Language
uThe binary object (strings of 0’s & 1’s) file is the only form a computer can be given software.
uComputers can be programmed to translate software expressed in other forms into binary object code.
nThis process includes as assembling.
uAssembly language is an alternative form of machine language that uses letters and normal numbers so people can understand it
1)Computer scans assembly code
2)As it encounters words it looks them up in a table to convert
to binary
3)Converts numbers to binary, then assembles the binary pieces into an instruction
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Programming Languages
uMost modern software is written in a high-level programming language
uHigh-level languages are compiled (translated) into assembly language, which is then assembled into binary
uThese languages are preferred because they have special statement forms that help programmers describe the complicated tasks they want done.
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Instruction Sets
uComputers do not understand Java by themselves nSeveral layers of software between your code and the
machine itself
uJava: machine independent high-level language
nRuns on anything with a JVM
nLanguage has many sophisticated features nCan do complex things with little code
uMachine Level: programs composed of complex combinations of simple “instructions”
uEach machine has a unique “instruction set” also known as ISA (Instruction Set Architecture)
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Instruction Sets
uThe instruction set is what the programmer “sees” and “uses”
uSet of operations that that CPU can execute
uEach MIPS instruction has 32-bit representation nBinary representation – machine code
nHuman readable assembly language
uHigh-level program, describe “what” and “how” uLow-level program, also specify “where”
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MIPS Instructions
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MIPS Assembly Language program for n!
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Very Simple Example
uHow to add two numbers?
uIn Java: a = b + c;
uIn MIPS assembly language, need to know: nWhere is b?
nWhere is c?
nWhere to put the result (where is a)?
nWhat instruction(s) should be used?
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Very Simple Example
ua = b + c
uWe need to
u Put b and c into the registers
u Load them from the memory u Add them together
u The result will go into a register
u Put the result into the memory location of a
u Store it
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Very Simple Example
Load b: Load c:
Add:
Store as a:
a=b+c
lw $8, &b
lw $9, &c
add $10, $8, $9
sw $10, &a
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Another Example
Load b: Load c: Load d: Add:
Sub:
Store as a:
a=b+c–d
lw $8, &b lw $9, &c
lw $10, &d
add $11, $8, $9 sub $11, $11, $10
sw $11, &a
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A Bit More Complex Example
Load a: Value 1: Ifa!= 1: b=0: jump: b=1: End:
L1: L2:
if (a == 1) b = 0;
else b = 1;
lw $8, &a
li $9, 1
bne $8, $9, L1 li $10, 0
j L2
li $10, 1
sw $10, &b
Some instructions use one register, some use two, some use three, some take values, some take addresses. How?
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MIPS Instruction Types
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A For Loop
y=0;
for (i=1; i<=x; i++) {
y = y + i; }
How can we write this in MIPS Assembly ?
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Summary
u We have revisited the von Neumann Architecture and compared it with Harvard Architecture.
u We have been introduced to pipelined execution of instructions.
u We’ve also seen some detail on MIPS R4000 and programmed it in its own language
u Examples of constructing “useful” programs at the machine level, as you learn to program in Java,
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