Chapter …
Memory
Hungwen Li
CMPE 120
COMPUTER ORGANIZATION AND DESIGN
The Hardware/Software Interface
COMPUTER ORGANIZATION AND DESIGN
The Hardware/Software Interface
Morgan Kaufmann Publishers
23 October, 2020
Chapter 4 — The Processor
1
Sequential Logic
Recall Combinational Logic
Consists of an acyclic network of logic gates
Continuously responds to changes in inputs
Outputs become (after a short delay) boolean functions of the inputs.
ALU/MUX/Instruction decoder
Sequential Logic
Combinational Logic
Memory
clock
output
input
state
Previous state
A group of logic elements that contain memory and hence whose output depends on the inputs as well as the current contents of the memory
Two input : R, S
Two output : Q and
Depending on R, S as well as themselves
Circular dependency
Flip Flop – Store 1 Bit
Case 1: R = 0, S = 0
Assume Q=0,
Q = 0 = 1 Qnext = 0
Flip Flop – Store 1 Bit
0
0
0
0
1
1
Qnext is the same as Q, a stable state
Case 1: R = 0, S = 0
Assume Q=0
Q = 0 = 1 Qnext = 0
Assume Q=1
Q = 1 = 0 Qnext = 1
Flip Flop – Store 1 Bit
0
0
1
1
0
0
Qnext is the same as Q, a stable state
When R=0 and S=0, Qnext takes same value as before.
Case 2: R = 1, S = 0
Q = ? Qnext = 0 and = 1
Flip Flop – Store 1 Bit
1
0
0
1
0
?
1
When R=1 and S=0, Qnext=0 and =1.
Case 3: R = 0, S = 1
Q = ? Qnext = 1 and = 0
Flip Flop – Store 1 Bit
0
1
0
1
0
?
1
When R=0 and S=1, Qnext=1 and =0.
Flip Flop – Store 1 Bit
It works to store 1 bit
Pulse (temporarily raise) the R (reset) input to record a 0.
Pulse the S (set) input to record a 1.
Otherwise Q signal will remain the same
But not very convenient to use in practice with 2 inputs
Characteristic table
S R Qnext Action
0 0 Q hold state
0 1 0 reset
1 0 1 set
1 1 ? not allowed
Ideal Memory to Store 1 Bit …
Ideal device for storing a bit
Place the bit to store on Data line.
Raise Enable to high (1) temporarily
E.g., a clock signal
The value on line Data is stored (or latched) in the device.
Lower Enable to low (0).
Reading Q returns the stored bit until next store.
Data
Q
Enable
Gated D Latch (or D Latch)
Add 2 AND gates in front of flip flop
“C” stands for “clock” (or “Enabled” in previous page)
Also denoted as CP (“Clock Pulse”)
“D” stands for “Data”
R
S
Gated D Latch (or D Latch)
Case 1 : C =0; D = ?
R=0, S=0 Q will hold its value in this state
R
S
C D R S Qnext notes
0 ? 0 0 Q Hold state
0
0
0
0
0
?
?
?
Gated D Latch (or D Latch)
Case 2 : C =1; D = 0
R=1 and S=0 Q will be set to 0
R
S
C D R S Qnext notes
0 ? 0 0 Q Hold state
1 0 1 0 0 Reset (0)
1
1
0
1
1
0
1
0
0
1
Gated D Latch (or D Latch)
Case 3 : C =1; D = 1
R=0 and S=1 Q will be set to 1
R
S
C D R S Qnext notes
0 ? 0 0 Q Hold state
1 0 1 0 0 Reset (0)
1 1 0 1 1 Set (1)
1
1
1
0
1
1
0
1
1
0
Gated D Latch (or D Latch)
_ Q
Q
D
C
Simplified representation for D latch
Clock Edge Triggering
Q only changes its value on the rising edge of clock pulse
Registers
Implement a 4-bit Register
Register is a small, fast, frequently accessed memory residing inside processor
Use 4 D latches
Share the same C input (or CP input) so that the values change in synchronization
This can be a global clock signal!
D0–D3 are the data input
Q0–Q3 are the output
How to implement a 32bit register?
Use 32 D latches sharing the same clock signal (C)
D
CP Q
_ Q
D
CP Q
_ Q
D
CP Q
_ Q
D
CP Q
_ Q
C
D2
D3
D1
D0
Q0
Q1
Q2
Q3
Register File
A register is made up of several flip flops or D latches , each of which provides storage and access for an individual bit.
A register file is made up of several registers and a control logic
For example, in MIPS there are 32 general purpose 32-bit registers
And we have a register file with 32 32-bit registers
Register File
Input
two 5-bit read register numbers
one 5-bit write register
32-bit data to write
One write signal (control signal)
5
5
5
32
32
32
Output
Two 32-bit read data
Why do we have 2 registers for reading?
Can read 2 register at a time;
(Or write to one register at a time)
Write to A Register
Set up “register number” and “register data”
Send “Write” pulse to perform write
Decoder output controls which register gets “Write” signal (i.e., C == 1)
All other registers will not have “Write” signal (i.e., C == 0)
5
32
Morgan Kaufmann Publishers
23 October, 2020
Chapter 4 — The Processor
22
Write to A Register
For example, for 32bit MIPS
Decoder has 5 input signals and 32 output signals (n==5)
suppose register number is 30 (111102)
1
111102
0
0
0
0
1
1
1
1
0
1
0
1
0
5
32
1
0
0
0
Read from Two Registers
This is combinational logic
Shortly after register numbers are setup, proper register data would appear on output
How many inputs to MUX for MIPS?
How many bits in each input?
5
5
32
32
RAM
(Random Access Memroy)
How Many Transistors in Gated D Latch?
Each AND/OR gate needs 2 transistors
Each NOT gate needs 1 transistor
We will have 11 transistors in total!
D latches are expensive for storing many bits!
Capacitor
A device that stores electrical energy in an electric field
It has 2 terminals.
When applied voltage, it maintains electric energy after removal of external voltage for a certain amount of time.
DRAM – Dynamic Random Access Memory
DRAM cell for storing 1 bit
A pass transistor controls on/off between capacitor and bit line
Value (0 or 1) is stored in capacitor (high/low voltage)
“bit line” is used to read/write
Only need 1 transistor per bit!
DRAM Cell – Write
0
DRAM Cell – Write
Apply data to write (0 or 1) on bit line
0 or 1
0
1
DRAM Cell – Write
Apply data to write (0 or 1) on bit line
Apply high voltage (1) to word line
0 or 1
1
DRAM Cell – Write
Apply data to write (0 or 1) on bit line
Apply high voltage (1) to word line
Capacitor will hold same value as bit line (0 or 1)
0 or 1
0 or 1
0
DRAM Cell – Write
Apply data to write (0 or 1) on bit line
Apply high voltage (1) to word line
Capacitor will hold same value as bit line (0 or 1)
Restore low voltage (0) to word line
Bit line can change its value, but capacitor will keep value for a while
In other words, capacitor remembers what bit line value was.
?
0 or 1
How do we read out the value remembered by capacitor?
DRAM Cell – Read
Apply high voltage (1) to word line
0
1
0 or 1
DRAM Cell – Read
Apply high voltage (1) to word line
Sense voltage on “bit line” (0 or 1)
0 or 1
0
1
0 or 1
DRAM Cell – Read
Apply high voltage (1) to word line
Sense voltage on “bit line” (0 or 1)
Restore low voltage (0) to word line
0 or 1
0
0 or 1
DRAM Cell – Read
Apply high voltage (1) to word line
Sense voltage on “bit line” (0 or 1)
Restore low voltage (0) to word line
But capacitor will drop to low voltage (0) – why?
0 or 1
0
0
DRAM Cell – Read
Apply high voltage (1) to word line
Sense voltage on “bit line” (0 or 1)
Restore low voltage (0) to word line
But capacitor will drop to low voltage (0) – why?
Because capacitor loses energy during “sensing”, i.e., connecting its terminal to ground
This is called destructive read of DRAM cell
0 or 1
0
0
Solution is to immediately write back the value being read.
DRAM Cell – Refresh
In fact, even without any READ operations, capacitor will lose its value over time.
Periodic refreshing (read and write back the read value) is needed
Typically <64ms per refresh (i.e., > 16 times/sec)
Hence the reason it is called “dynamic” RAM (“dynamically refreshing”)
Storing Multiple Bits
Chain 32 cells together on a single word line
And they will be read/written/refreshed as a whole
Adding proper addressing logic (decoders) can construct multi-word memory system
DRAM incented by Robert Dennard
DRAM Summary
Conceptually, a large array where each row (1 byte) is uniquely addressable.
Characteristics
Dynamic RAM (DRAM) is large, inexpensive, but relatively slow.
1 transistor and 1 capacitor per bit.
Reads are destructive. Requires periodic refresh.
Access time takes hundreds of CPU cycles.
Used for system main memory
Memory
address
data
Static Random Access Memory (SRAM)
Static (SRAM) is faster but more expensive.
Similar to D latch
Uses 6 transistors per bit.
Typically used for cache memory
Which is faster than DRAM, but slower than register
Reference Readings
Patterson, “Computer Organization and Design”
Appendix B.8, B.9
Tanenbaum, “Structured Computer Organization”
Sec 3.3
/docProps/thumbnail.jpeg