Impress
CMPSC-F353
Architecture of Comp Systems
Microprogramming , CPU
Instruction format:
Microinstruction format:
Microprogram Example
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 224
Fetch (Sub)Routine
Memory Map(128 words) :
Address 0 to 63 : Routines for the 16 instructions(4 instructions)
Address 64 to 127 : Any other purpose(Subroutines : FETCH, INDRCT)
Microinstructions for FETCH Subroutine
Fetch Subroutine : address 64
Opcode Fetch
Opcode Decode
I Opcode Address
15 14 11 10 …. … 0
Mapping
Operand Address
Instruction Format
Microprogram Example
Symbolic Microprogram :
The execution of MAP microinstruction in FETCH subroutine
Branch to address 0xxxx00 (xxxx = 4 bit Opcode)
ADD : 0 0000 00 = 0
BRANCH : 0 0001 00 = 4
STORE : 0 0010 00 = 8
EXCHANGE : 0 0011 00 = 12, ( 16, 20, … , 60 )
Indirect Address : I = 1
Indirect Addressing :
INDRCT subroutine
Execution of Instruction
Microprogram Example
Symbolic Microprogram
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 228
Symbolic microprogram must be translated to binary either by means of an assembler program or by the user
Binary Microprogram
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 230
Central Processing Unit
3 major parts of CPU :
1) Register Set
2) ALU
3) Control
Design Examples of simple CPU
Hardwired Control : Chap. 5
Microprogrammed Control : Chap. 7
In this chapter : Chap. 8
Describe the organization and architecture of the CPU with an emphasis on the user’s view of the computer
User who programs the computer in machine/assembly language must be aware of
1) Instruction Formats
2) Addressing Modes
3) Register Sets
Computer Architecture as seen by the programmer
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 242
Memory locations are needed for storing pointers, counters, return address, temporary results, and partial products during multiplication
Memory access is the most time-consuming operation in a computer
More convenient and efficient way is to store intermediate values in processor registers
General Register Organization
Bus organization for 7 CPU registers :
2 MUX : select one of 7 register or external data input by SELA and SELB
BUS A and BUS B : form the inputs to a common ALU
ALU : OPR determine the arithmetic or logic microoperation
The result of the microoperation is available for external data output and also goes into the inputs of all the registers
3 X 8 Decoder : select the register (by SELD) that receives the information from ALU
External Output
External Input
General Register Organization
Binary selector input :
1) MUX A selector (SELA) : to place the content of R2 into BUS A
2) MUX B selector (SELB) : to place the content of R3 into BUS B
3) ALU operation selector (OPR) : to provide the arithmetic addition R2 + R3
4) Decoder selector (SELD) : to transfer the content of the output bus into R1
Control Word
14 bit control word (4 fields):
SELA (3 bits) : select a source register for the A input of the ALU
SELB (3 bits) : select a source register for the B input of the ALU
SELD (3 bits) : select a destination register using the 3 X 8 decoder
OPR (5 bits) : select one of the operations in the ALU
General Register Organization
Encoding of Register Selection Fields :
SELA or SELB = 000 (Input) : MUX selects the external input data
SELD = 000 (None) : no destination register is selected but the contents of the output bus are available in the external output
Encoding of ALU Operation (OPR) :
General Register Organization
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 245
Examples of Microoperations:
TSFA (Transfer A) :
XOR :
Examples of Microoperations
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 246
What’s next?
HW#6 is due on Tuesday 29th
HW#7 is due on Monday 4th
Exam#2 is on Wednesday 6th
Reading:
Chapter 7:
Section 7.3
Chapter 8:
Section 8.1 to 8.2
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