ALU Instructions
MIPS Arithmetic
and Logic Instructions
COE 301
Computer Organization
Prof. Muhamed Mudawar
College of Computer Sciences and Engineering
King Fahd University of Petroleum and Minerals
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Presentation Outline
Overview of the MIPS Architecture
R-Type Instruction Format
R-type Arithmetic, Logical, and Shift Instructions
I-Type Instruction Format and Immediate Constants
I-type Arithmetic and Logical Instructions
Pseudo Instructions
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Overview of the MIPS Architecture
Memory
Up to 232 bytes = 230 words
4 bytes per word
$0
$1
$2
$31
Hi
Lo
ALU
F0
F1
F2
F31
FP
Arith
EPC
Cause
BadVaddr
Status
EIU
FPU
TMU
Execution &
Integer Unit
(Main proc)
Floating
Point Unit
(Coproc 1)
Trap &
Memory Unit
(Coproc 0)
. . .
. . .
Integer
mul/div
Arithmetic &
Logic Unit
32 General
Purpose
Registers
Integer Multiplier/Divider
32 Floating-Point
Registers
Floating-Point
Arithmetic Unit
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
MIPS General-Purpose Registers
32 General Purpose Registers (GPRs)
All registers are 32-bit wide in the MIPS 32-bit architecture
Software defines names for registers to standardize their use
Assembler can refer to registers by name or by number ($ notation)
Name Register Usage
$zero $0 Always 0 (forced by hardware)
$at $1 Reserved for assembler use
$v0 – $v1 $2 – $3 Result values of a function
$a0 – $a3 $4 – $7 Arguments of a function
$t0 – $t7 $8 – $15 Temporary Values
$s0 – $s7 $16 – $23 Saved registers (preserved across call)
$t8 – $t9 $24 – $25 More temporaries
$k0 – $k1 $26 – $27 Reserved for OS kernel
$gp $28 Global pointer (points to global data)
$sp $29 Stack pointer (points to top of stack)
$fp $30 Frame pointer (points to stack frame)
$ra $31 Return address (used for function call)
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Instruction Categories
Integer Arithmetic (our focus in this presentation)
Arithmetic, logic, and shift instructions
Data Transfer
Load and store instructions that access memory
Data movement and conversions
Jump and Branch
Flow-control instructions that alter the sequential sequence
Floating Point Arithmetic
Instructions that operate on floating-point registers
Miscellaneous
Instructions that transfer control to/from exception handlers
Memory management instructions
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Next . . .
Overview of the MIPS Architecture
R-Type Instruction Format
R-type Arithmetic, Logical, and Shift Instructions
I-Type Instruction Format and Immediate Constants
I-type Arithmetic and Logical Instructions
Pseudo Instructions
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
R-Type Instruction Format
Op: operation code (opcode)
Specifies the operation of the instruction
Also specifies the format of the instruction
funct: function code – extends the opcode
Up to 26 = 64 functions can be defined for the same opcode
MIPS uses opcode 0 to define many R-type instructions
Three Register Operands (common to many instructions)
Rs, Rt: first and second source operands
Rd: destination operand
sa: the shift amount used by shift instructions
Op6
Rs5
Rt5
Rd5
funct6
sa5
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
R-Type Integer Add and Subtract
Instruction Meaning Op Rs Rt Rd sa func
add $t1, $t2, $t3 $t1 = $t2 + $t3 0 $t2 $t3 $t1 0 0x20
addu $t1, $t2, $t3 $t1 = $t2 + $t3 0 $t2 $t3 $t1 0 0x21
sub $t1, $t2, $t3 $t1 = $t2 – $t3 0 $t2 $t3 $t1 0 0x22
subu $t1, $t2, $t3 $t1 = $t2 – $t3 0 $t2 $t3 $t1 0 0x23
add, sub: arithmetic overflow causes an exception
In case of overflow, result is not written to destination register
addu, subu: arithmetic overflow is ignored
addu, subu: compute the same result as add, sub
Many programming languages ignore overflow
The + operator is translated into addu
The – operator is translated into subu
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Bits have NO meaning. The same n bits stored in a register can represent an unsigned or a signed integer.
Unsigned Integers: n-bit representation
Signed Integers: n-bit 2’s complement representation
Range, Carry, Borrow, and Overflow
max = 2n–1
min = 0
Carry = 1
Addition
Numbers > max
Borrow = 1
Subtraction
Numbers < 0
Positive
Overflow
Numbers > max
Negative
Overflow
Numbers < min
max = 2n-1–1
Finite Set of Signed Integers
0
min = -2n-1
Finite Set of Unsigned Integers
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Carry and Overflow
Carry is useful when adding (subtracting) unsigned integers
Carry indicates that the unsigned sum is out of range
Overflow is useful when adding (subtracting) signed integers
Overflow indicates that the signed sum is out of range
Range for 32-bit unsigned integers = 0 to (232 – 1)
Range for 32-bit signed integers = -231 to (231 – 1)
11111 1 1 11 1
1000 0100 0000 0000 1110 0001 0100 0001
1111 1111 0000 0000 1111 0101 0010 0000
1000 0011 0000 0001 1101 0110 0110 0001
+
Example 1: Carry = 1, Overflow = 0 (NO overflow)
Unsigned sum is out-of-range, but the Signed sum is correct
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
More Examples of Carry and Overflow
Example 2: Carry = 0, Overflow = 1
01111 1 11 1
0010 0100 0000 0100 1011 0001 0100 0100
0111 1111 0111 0000 0011 0101 0000 0010
1010 0011 0111 0100 1110 0110 0100 0110
+
Unsigned sum is correct, but the Signed sum is out-of-range
Example 3: Carry = 1, Overflow = 1
1 11 1 11 1
1000 0100 0000 0100 1011 0001 0100 0100
1001 1111 0111 0000 0011 0101 0000 0010
0010 0011 0111 0100 1110 0110 0100 0110
+
Both the Unsigned and Signed sums are out-of-range
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Using Add / Subtract Instructions
Consider the translation of: f = (g+h)–(i+j)
Programmer / Compiler allocates registers to variables
Given that: $t0=f, $t1=g, $t2=h, $t3=i, and $t4=j
Called temporary registers: $t0=$8, $t1=$9, …
Translation of: f = (g+h)–(i+j)
addu $t5, $t1, $t2 # $t5 = g + h
addu $t6, $t3, $t4 # $t6 = i + j
subu $t0, $t5, $t6 # f = (g+h)–(i+j)
Assembler translates addu $t5,$t1,$t2 into binary code
000000
Op
01001
$t1
01010
$t2
01101
$t5
00000
sa
100001
addu
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Logic Bitwise Operations
Logic bitwise operations: and, or, xor, nor
AND instruction is used to clear bits: x and 0 0
OR instruction is used to set bits: x or 1 1
XOR instruction is used to toggle bits: x xor 1 not x
NOT instruction is not needed, why?
not $t1, $t2 is equivalent to: nor $t1, $t2, $t2
x
0
0
1
1
y
0
1
0
1
x and y
0
0
0
1
x
0
0
1
1
y
0
1
0
1
x or y
0
1
1
1
x
0
0
1
1
y
0
1
0
1
x xor y
0
1
1
0
x
0
0
1
1
y
0
1
0
1
x nor y
1
0
0
0
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Logic Bitwise Instructions
Instruction Meaning Op Rs Rt Rd sa func
and $t1, $t2, $t3 $t1 = $t2 & $t3 0 $t2 $t3 $t1 0 0x24
or $t1, $t2, $t3 $t1 = $t2 | $t3 0 $t2 $t3 $t1 0 0x25
xor $t1, $t2, $t3 $t1 = $t2 ^ $t3 0 $t2 $t3 $t1 0 0x26
nor $t1, $t2, $t3 $t1 = ~($t2|$t3) 0 $t2 $t3 $t1 0 0x27
Examples:
Given: $t1 = 0xabcd1234 and $t2 = 0xffff0000
and $t0, $t1, $t2
# $t0 = 0xabcd0000
or $t0, $t1, $t2
# $t0 = 0xffff1234
xor $t0, $t1, $t2
# $t0 = 0x54321234
nor $t0, $t1, $t2
# $t0 = 0x0000edcb
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Shift Operations
Shifting is to move the 32 bits of a number left or right
sll means shift left logical (insert zero from the right)
srl means shift right logical (insert zero from the left)
sra means shift right arithmetic (insert sign-bit)
The 5-bit shift amount field is used by these instructions
shift-in 0
. . .
shift-out
sll
32-bit value
. . .
shift-in 0
shift-out
srl
. . .
shift-in sign-bit
shift-out
sra
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Shift Instructions
sll, srl, sra: shift by a constant amount
The shift amount (sa) field specifies a number between 0 and 31
sllv, srlv, srav: shift by a variable amount
A source register specifies the variable shift amount between 0 and 31
Only the lower 5 bits of the source register is used as the shift amount
Instruction Meaning Op Rs Rt Rd sa func
sll $t1,$t2,10 $t1 = $t2 << 10 0 0 $t2 $t1 10 0
srl $t1,$t2,10 $t1 = $t2 >>> 10 0 0 $t2 $t1 10 2
sra $t1,$t2,10 $t1 = $t2 >> 10 0 0 $t2 $t1 10 3
sllv $t1,$t2,$t3 $t1 = $t2 << $t3 0 $t3 $t2 $t1 0 4
srlv $t1,$t2,$t3 $t1 = $t2 >>>$t3 0 $t3 $t2 $t1 0 6
srav $t1,$t2,$t3 $t1 = $t2 >> $t3 0 $t3 $t2 $t1 0 7
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
$t1 = 0x0000abcd
$t1 = 0xcd123400
Shift Instruction Examples
Given that: $t2 = 0xabcd1234 and $t3 = 16
sll $t1, $t2, 8
sra $t1, $t2, 4
$t1 = 0xfabcd123
srlv $t1, $t2, $t3
Rt = $t2
Op
Rs = $t3
Rd = $t1
sa
srlv
01010
000000
01011
01001
00000
000110
srl $t1, $t2, 4
$t1 = 0x0abcd123
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Binary Multiplication
Shift Left Instruction (sll) can perform multiplication
When the multiplier is a power of 2
You can factor any binary number into powers of 2
Example: multiply $t0 by 36
$t0*36 = $t0*(4 + 32) = $t0*4 + $t0*32
sll $t1, $t0, 2 # $t1 = $t0 * 4
sll $t2, $t0, 5 # $t2 = $t0 * 32
addu $t3, $t1, $t2 # $t3 = $t0 * 36
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Your Turn . . .
sll $t1, $t0, 1 # $t1 = $t0 * 2
sll $t2, $t0, 3 # $t2 = $t0 * 8
sll $t3, $t0, 4 # $t3 = $t0 * 16
addu $t4, $t1, $t2 # $t4 = $t0 * 10
addu $t5, $t4, $t3 # $t5 = $t0 * 26
Multiply $t0 by 26, using shift and add instructions
Hint: 26 = 2 + 8 + 16
Multiply $t0 by 31, Hint: 31 = 32 – 1
sll $t1, $t0, 5 # $t1 = $t0 * 32
subu $t2, $t1, $t0 # $t2 = $t0 * 31
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Next . . .
Overview of the MIPS Architecture
R-Type Instruction Format
R-type Arithmetic, Logical, and Shift Instructions
I-Type Instruction Format and Immediate Constants
I-type Arithmetic and Logical Instructions
Pseudo Instructions
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
I-Type Instruction Format
Constants are used quite frequently in programs
The R-type shift instructions have a 5-bit shift amount constant
What about other instructions that need a constant?
I-Type: Instructions with Immediate Operands
16-bit immediate constant is stored inside the instruction
Rs is the source register number
Rt is now the destination register number (for R-type it was Rd)
Examples of I-Type ALU Instructions:
Add immediate: addi $t1, $t2, 5 # $t1 = $t2 + 5
OR immediate: ori $t1, $t2, 5 # $t1 = $t2 | 5
Op6
Rs5
Rt5
immediate16
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
I-Type ALU Instructions
Instruction Meaning Op Rs Rt Immediate
addi $t1, $t2, 25 $t1 = $t2 + 25 0x8 $t2 $t1 25
addiu $t1, $t2, 25 $t1 = $t2 + 25 0x9 $t2 $t1 25
andi $t1, $t2, 25 $t1 = $t2 & 25 0xc $t2 $t1 25
ori $t1, $t2, 25 $t1 = $t2 | 25 0xd $t2 $t1 25
xori $t1, $t2, 25 $t1 = $t2 ^ 25 0xe $t2 $t1 25
lui $t1, 25 $t1 = 25 << 16 0xf 0 $t1 25
addi: overflow causes an arithmetic exception
In case of overflow, result is not written to destination register
addiu: same operation as addi but overflow is ignored
Immediate constant for addi and addiu is signed
No need for subi or subiu instructions
Immediate constant for andi, ori, xori is unsigned
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Given that registers $t0, $t1, $t2 are used for A, B, C
Examples of I-Type ALU Instructions
Expression Equivalent MIPS Instruction
A = B + 5;
C = B – 1;
A = B & 0xf;
C = B | 0xf;
C = 5;
A = B;
addiu $t0, $t1, 5
addiu $t2, $t1, -1
andi $t0, $t1, 0xf
ori $t2, $t1, 0xf
addiu $t2, $zero, 5
addiu $t0, $t1, 0
No need for subiu, because addiu has signed immediate
Register $zero has always the value 0
Rt = $t2
Op = addiu
Rs = $t1
-1 = 0b1111111111111111
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
23
I-Type instructions can have only 16-bit constants
What if we want to load a 32-bit constant into a register?
Can’t have a 32-bit constant in I-Type instructions
The sizes of all instructions are fixed to 32 bits
Solution: use two instructions instead of one
Suppose we want: $t1 = 0xAC5165D9 (32-bit constant)
lui: load upper immediate
32-bit Constants
Op6
Rs5
Rt5
immediate16
lui $t1, 0xAC51
ori $t1, $t1, 0x65D9
0xAC51
$t1
Upper
16 bits
0x0000
Lower
16 bits
0xAC51
$t1
0x65D9
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
24
Pseudo-Instructions
Introduced by the assembler as if they were real instructions
Facilitate assembly language programming
Pseudo-Instruction Equivalent MIPS Instruction
move $t1, $t2
not $t1, $t2
neg $t1, $t2
li $t1, -5
li $t1, 0xabcd1234
The MARS tool has a long list of pseudo-instructions
addu $t1, $t2, $zero
nor $t1, $t2, $zero
sub $t1, $zero, $t2
lui $t1, 0xabcd
ori $t1, $t1, 0x1234
addiu $t1, $zero, -5
MIPS Instruction Set Architecture COE 301 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
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