Control Flow and Arrays
Control Flow and Arrays
COE 301
Computer Organization
Prof. Muhamed Mudawar
College of Computer Sciences and Engineering
King Fahd University of Petroleum and Minerals
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Presentation Outline
Control Flow: Branch and Jump Instructions
Translating If Statements and Boolean Expressions
Arrays
Load and Store Instructions
Translating Loops and Traversing Arrays
Addressing Modes
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Control Flow
High-level programming languages provide constructs:
To make decisions in a program: IF-ELSE
To repeat the execution of a sequence of instructions: LOOP
The ability to make decisions and repeat a sequence of instructions distinguishes a computer from a calculator
All computer architectures provide control flow instructions
Essential for making decisions and repetitions
These are the conditional branch and jump instructions
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
MIPS compare and branch instructions:
beq Rs, Rt, label if (Rs == Rt) branch to label
bne Rs, Rt, label if (Rs != Rt) branch to label
MIPS compare to zero & branch instructions:
Compare to zero is used frequently and implemented efficiently
bltz Rs, label if (Rs < 0) branch to label
bgtz Rs, label if (Rs > 0) branch to label
blez Rs, label if (Rs <= 0) branch to label
bgez Rs, label if (Rs >= 0) branch to label
beqz and bnez are defined as pseudo-instructions.
MIPS Conditional Branch Instructions
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
4
Branch Instruction Format
The branch instructions modify the PC register only
PC-Relative addressing:
If (branch is taken) PC = PC + 4 + 4×offset else PC = PC+4
Branch Instructions are of the I-type Format:
Op6
Rs5
Rt5
16-bit offset
Instruction I-Type Format
beq Rs, Rt, label Op = 4 Rs Rt 16-bit Offset
bne Rs, Rt, label Op = 5 Rs Rt 16-bit Offset
blez Rs, label Op = 6 Rs 0 16-bit Offset
bgtz Rs, label Op = 7 Rs 0 16-bit Offset
bltz Rs, label Op = 1 Rs 0 16-bit Offset
bgez Rs, label Op = 1 Rs 1 16-bit Offset
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Unconditional Jump Instruction
The unconditional Jump instruction has the following syntax:
j label # jump to label
. . .
label:
The jump instruction is always taken
The Jump instruction is of the J-type format:
The jump instruction modifies the program counter PC:
The upper 4 bits of the PC are unchanged
Op6 = 2
26-bit address
26-bit address
00
PC4
multiple of 4
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Translating an IF Statement
Consider the following IF statement:
if (a == b) c = d + e; else c = d – e;
Given that a, b, c, d, e are in $t0 … $t4 respectively
How to translate the above IF statement?
bne $t0, $t1, else
addu $t2, $t3, $t4
j next
else: subu $t2, $t3, $t4
next: . . .
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Logical AND Expression
Programming languages use short-circuit evaluation
If first condition is false, second condition is skipped
if (($t1 > 0) && ($t2 < 0)) {$t3++;}
# One Possible Translation ...
bgtz $t1, L1 # first condition
j next # skip if false
L1: bltz $t2, L2 # second condition
j next # skip if false
L2: addiu $t3, $t3, 1 # both are true
next:
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Better Translation of Logical AND
Allow the program to fall through to second condition
!($t1 > 0) is equivalent to ($t1 <= 0)
!($t2 < 0) is equivalent to ($t2 >= 0)
Number of instructions is reduced from 5 to 3
if (($t1 > 0) && ($t2 < 0)) {$t3++;}
# Better Translation ...
blez $t1, next # 1st condition false?
bgez $t2, next # 2nd condition false?
addiu $t3, $t3, 1 # both are true
next:
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Logical OR Expression
Short-circuit evaluation for logical OR
If first condition is true, second condition is skipped
Use fall-through to keep the code as short as possible
bgtz $t1, L1 # 1st condition true?
bgez $t2, next # 2nd condition false?
L1: addiu $t3, $t3, 1 # increment $t3
next:
if (($t1 > 0) || ($t2 < 0)) {$t3++;}
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Compare Instructions
MIPS also provides set less than instructions
slt Rd, Rs, Rt if (Rs < Rt) Rd = 1 else Rd = 0
sltu Rd, Rs, Rt unsigned <
slti Rt, Rs, imm if (Rs < imm) Rt = 1 else Rt = 0
sltiu Rt, Rs, imm unsigned <
Signed / Unsigned comparisons compute different results
Given that: $t0 = 1 and $t1 = -1 = 0xffffffff
slt $t2, $t0, $t1 computes $t2 = 0
sltu $t2, $t0, $t1 computes $t2 = 1
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Compare Instruction Formats
The other comparisons are defined as pseudo-instructions:
seq, sne, sgt, sgtu, sle, sleu, sge, sgeu
Instruction Meaning Format
slt Rd, Rs, Rt Rd=(Rs = $t5)) {
$t3 = $t4 + $t5;
}
bgt $t3, $t4, L1
blt $t4, $t5, L1
addu $t3, $t4, $t5
L1:
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Conditional Move Instructions
Conditional move can eliminate branch & jump instructions
Instruction Meaning R-Type Format
movz Rd, Rs, Rt if (Rt==0) Rd=Rs Op=0 Rs Rt Rd 0 0xa
movn Rd, Rs, Rt if (Rt!=0) Rd=Rs Op=0 Rs Rt Rd 0 0xb
if ($t0 == 0) {$t1=$t2+$t3;} else {$t1=$t2-$t3;}
bne $t0, $0, L1
addu $t1, $t2, $t3
j L2
L1: subu $t1, $t2, $t3
L2: . . .
addu $t1, $t2, $t3
subu $t4, $t2, $t3
movn $t1, $t4, $t0
. . .
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Next . . .
Control Flow: Branch and Jump Instructions
Translating If Statements and Boolean Expressions
Arrays
Load and Store Instructions
Translating Loops and Traversing Arrays
Addressing Modes
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Arrays
In a high-level programming language, an array is a homogeneous data structure with the following properties:
All array elements are of the same type and size
Once an array is allocated, its size cannot be modified
The base address is the address of the first array element
The array elements can be indexed
The address of any array element can be computed
In assembly language, an array is just a block of memory
In fact, all objects are simply blocks of memory
The memory block can be allocated statically or dynamically
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Static Array Allocation
An array can be allocated statically in the data segment
A data definition statement allocates static memory:
label: .type value0 [, value1 …]
label: is the name of the array
.type directive specifies the size of each array element
value0, value1 … specify a list of initial values
Examples of static array definitions:
arr1: .half 20, -1 # array of 2 half words
arr2: .word 1:5 # array of 5 words (value=1)
arr3: .space 20 # array of 20 bytes
str1: .asciiz “Null-terminated string”
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Watching Values in the Data Segment
The labels window is the symbol table
Shows labels and corresponding addresses
The la pseudo-instruction loads the address of any label into a register
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Dynamic Memory Allocation
One of the functions of the OS is to manage memory
A program can allocate memory on the heap at runtime
The heap is part of the data segment that can grow at runtime
The program makes a system call ($v0=9) to allocate memory
.text
. . .
li $a0, 100 # $a0 = number of bytes to allocate
li $v0, 9 # system call 9
syscall # allocate 100 bytes on the heap
move $t0, $v0 # $t0 = address of allocated block
. . .
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Allocating Dynamic Memory on the Heap
Stack Segment
Heap Area
Static Area
Data Segment
0x00000000
Reserved
0x10000000
Text Segment
0x7fffffff
0x00400000
0x10040000
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Computing the Addresses of Elements
In a high-level programming language, an array is indexed
array[0] is the first element in the array
array[i] is the element at index i
&array[i] is the address of the element at index i
&array[i] = &array + i × element_size
For a 2D array, the array is stored linearly in memory
matrix[Rows][Cols] has (Rows × Cols) elements
&matrix[i][j] = &matrix + (i×Cols + j) × element_size
For example, to allocate a matrix[10][20] of integers:
matrix: .word 0:200 # 200 words (initialized to 0)
&matrix[1][5] = &matrix + (1×20 + 5)×4 = &matrix + 100
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Element Addresses in a 2D Array
&matrix[i][j] = &matrix + (i×COLS + j) × Element_size
0
1
…
i
…
ROWS-1
0
1
…
j
…
COLS-1
COLS
ROWS
Address calculation is essential when programming in assembly
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Load and Store Instructions
Instructions that transfer data between memory & registers
Programs include variables such as arrays and objects
These variables are stored in memory
Load Instruction:
Transfers data from memory to a register
Store Instruction:
Transfers data from a register to memory
Memory address must be specified by load and store
Memory
Registers
load
store
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Load Word Instruction (Word = 4 bytes in MIPS)
lw Rt, imm(Rs) # Rt MEMORY[Rs+imm]
Store Word Instruction
sw Rt, imm(Rs) # Rt MEMORY[Rs+imm]
Base / Displacement addressing is used
Memory Address = Rs (base) + Immediate (displacement)
Immediate16 is sign-extended to have a signed displacement
Load and Store Word
Op6
Rs5
Rt5
immediate16
Base or Displacement Addressing
Memory Word
Base address
+
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Example on Load & Store
Translate: A[1] = A[2] + 5 (A is an array of words)
Given that the address of array A is stored in register $t0
lw $t1, 8($t0) # $t1 = A[2]
addiu $t2, $t1, 5 # $t2 = A[2] + 5
sw $t2, 4($t0) # A[1] = $t2
Index of A[2] and A[1] should be multiplied by 4. Why?
Registers
sw
lw
Memory
A[2]
A[1]
A[3]
. . .
. . .
&A + 12
&A + 8
&A + 4
&A
$t0
$t1
$t2
&A
A[2]
A[2] + 5
. . .
. . .
A[0]
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
0
0
s
s
s
s
s
0
0
s
bu
b
h
hu
sign – extend
zero – extend
sign – extend
zero – extend
32-bit Register
The MIPS processor supports the following data formats:
Byte = 8 bits, Half word = 16 bits, Word = 32 bits
Load & store instructions for bytes and half words
lb = load byte, lbu = load byte unsigned, sb = store byte
lh = load half, lhu = load half unsigned, sh = store halfword
Load expands a memory value to fit into a 32-bit register
Store reduces a 32-bit register value to fit in memory
Load and Store Byte and Halfword
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Load and Store Instructions
Instruction Meaning I-Type Format
lb Rt, imm(Rs) Rt 1 MEM[Rs+imm] 0x20 Rs Rt 16-bit immediate
lh Rt, imm(Rs) Rt 2 MEM[Rs+imm] 0x21 Rs Rt 16-bit immediate
lw Rt, imm(Rs) Rt 4 MEM[Rs+imm] 0x23 Rs Rt 16-bit immediate
lbu Rt, imm(Rs) Rt 1 MEM[Rs+imm] 0x24 Rs Rt 16-bit immediate
lhu Rt, imm(Rs) Rt 2 MEM[Rs+imm] 0x25 Rs Rt 16-bit immediate
sb Rt, imm(Rs) Rt 1 MEM[Rs+imm] 0x28 Rs Rt 16-bit immediate
sh Rt, imm(Rs) Rt 2 MEM[Rs+imm] 0x29 Rs Rt 16-bit immediate
sw Rt, imm(Rs) Rt 4 MEM[Rs+imm] 0x2b Rs Rt 16-bit immediate
Base / Displacement Addressing is used
Memory Address = Rs (Base) + Immediate (displacement)
If Rs is $zero then Address = Immediate (absolute)
If Immediate is 0 then Address = Rs (register indirect)
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Next . . .
Control Flow: Branch and Jump Instructions
Translating If Statements and Boolean Expressions
Arrays
Load and Store Instructions
Translating Loops and Traversing Arrays
Addressing Modes
Control Flow and Arrays COE 301 / ICS 233 – Computer Organization – KFUPM © Muhamed Mudawar – slide ‹#›
Translating a WHILE Loop
Consider the following WHILE loop:
i = 0; while (A[i] != value && i