PowerPoint 演示文稿
CO101
Principle of Computer
Organization
Lecture 09: Single Cycle
Processor 2
Liang Yanyan
澳門科技大學
Macau of University of Science and Technology
Recap: A Single Cycle Datapath
• We have everything except control signals, this lecture will show you how to
generate the control signals.
2
Read
Address
Instr[31-0]
Instruction
Memory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read
Data 1
Read
Data 2
ALU
zero
RegWrite
Data
Memory
Address
Write Data
Read Data
MemWrite
MemRead
Sign
Extend 16 32
MemtoReg
ALUsrc
Shift
left 2
Add
PCsrc
RegDst
1
1
1
0
0
0
0
1
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15-11]
Shift
left 2
0
1
32
Instr[25-0]
26
PC+4[31-28]
28
Jump
ALUctr
SignExt
The Big Picture: Where are We Now?
• The Five Classic Components of a Computer
• Today’s Topic: Designing the Control for the Single Cycle
Datapath
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Control
Datapath
Memory
Processor
Input
Output
Step 4: Designing control signals
• Control signals are used to control the datapath to
perform necessary operations.
• Need to decide what control signals are required such
that we can fully control our processor to perform
calculation.
• Example: add t0, t1, t2
• Need the ALU to perform addition.
• As a result, we need a control signal “ALUctr” to control the ALU
to perform necessary operation.
4
Adding the Control
• Selecting the operations to perform (ALU, Register File
and Memory read/write)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the instruction
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Observations
op field always in bits 31-26
addr of two registers to be read are always specified by the rs and rt
fields (bits 25-21 and 20-16)
base register for lw and sw always in rs (bits 25-21)
addr. of register to be written is in one of two places – in rt(bits 20-
16) for lw; in rd (bits 15-11) for R-type instructions
offset for beq, lw, and sw always in bits 15-0
(Almost) Complete Single Cycle Datapath
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Meaning of the Control Signals
• RegDst: Register destination. 0 → rt, 1 → rd.
• RegWrite: Write register file or not. 0 → no, 1 → yes.
• ALUctr: Operation of ALU, “add”, “sub”, “or”, etc.
• ALUsrc: Select data for ALU. 0 → Register file, 1 →
Immediate.
• MemWrite: Write data memory or not. 0 → no, 1 → yes.
• MemRead: Read data memory or not. 0 → no, 1 → yes.
• MemtoReg: Select data for writing register file. 0 → ALU,
1 → data memory.
• PCsrc: Branch or not. 0 → no, 1 → yes.
• Jump: Jump or not. 0 → no, 1 → yes.
• SignExt: Perform sign or zero extend. “sign” or “zero”.
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Steps in add instruction
• add rd, rs, rt
• mem[PC] Fetch the instruction
from memory
• R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address 8 op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits The Single Cycle Datapath during add 9 • R[rd] <- R[rs] + R[rt] op rs rt rd shamt funct 0 6 11 16 21 26 31 Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero RegWrite=1 Data Memory Address Write Data Read Data MemWrite=0 MemRead=x Sign Extend 16 32 MemtoReg=0 ALUsrc=0 Shift left 2 Add PCsrc=0 RegDst=1 1 1 1 0 0 0 0 1 Instr[15-0] Instr[25-21] Instr[20-16] Instr[15-11] Shift left 2 0 1 32 Instr[25-0] 26 PC+4[31-28] 28 Jump=0 ALUctr=add x: means we don’t care SignExt=x The Single Cycle Datapath during sub?? 10 • R[rd] <- R[rs] - R[rt] (sub rd, rs, rt) op rs rt rd shamt funct 0 6 11 16 21 26 31 Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero RegWrite= Data Memory Address Write Data Read Data MemWrite= MemRead= Sign Extend 16 32 MemtoReg= ALUsrc= Shift left 2 Add PCsrc= RegDst= 1 1 1 0 0 0 0 1 Instr[15-0] Instr[25-21] Instr[20-16] Instr[15-11] Shift left 2 0 1 32 Instr[25-0] 26 PC+4[31-28] 28 Jump= ALUctr= SignExt= The Single Cycle Datapath during addi 11 • R[rt] <- R[rs] or SignExt[imm16] (addi t0, t1, -10) op rs rt immediate 0 16 21 26 31 Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero RegWrite=1 Data Memory Address Write Data Read Data MemWrite=0 MemRead=x Sign Extend 16 32 MemtoReg=0 ALUsrc=1 Shift left 2 Add PCsrc=0 RegDst=0 1 1 1 0 0 0 0 1 Instr[15-0] Instr[25-21] Instr[20-16] Instr[15-11] Shift left 2 0 1 32 Instr[25-0] 26 PC+4[31-28] 28 Jump=0 ALUctr=add SignExt=sign The Single Cycle Datapath during Load 12 • R[rt] <- Data Memory {R[rs] + SignExt[imm16]} lw rt, imm16(rs) op rs rt immediate 0 16 21 26 31 Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero RegWrite=1 Data Memory Address Write Data Read Data MemWrite=0 MemRead=1 Sign Extend 16 32 MemtoReg=1 ALUsrc=1 Shift left 2 Add PCsrc=0 RegDst=0 1 1 1 0 0 0 0 1 Instr[15-0] Instr[25-21] Instr[20-16] Instr[15-11] Shift left 2 0 1 32 Instr[25-0] 26 PC+4[31-28] 28 Jump=0 ALUctr=add SignExt=sign The Single Cycle Datapath during Store?? 13 • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] sw rt, imm16(rs) op rs rt immediate 0 16 21 26 31 Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero RegWrite= Data Memory Address Write Data Read Data MemWrite= MemRead= Sign Extend 16 32 MemtoReg= ALUsrc= Shift left 2 Add PCsrc= RegDst= 1 1 1 0 0 0 0 1 Instr[15-0] Instr[25-21] Instr[20-16] Instr[15-11] Shift left 2 0 1 32 Instr[25-0] 26 PC+4[31-28] 28 Jump= ALUctr= SignExt= The Single Cycle Datapath during Store 14 • Data Memory {R[rs] + SignExt[imm16]} <- R[rt] sw rt, imm16(rs) op rs rt immediate 0 16 21 26 31 Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero RegWrite=0 Data Memory Address Write Data Read Data MemWrite=1 MemRead=x Sign Extend 16 32 MemtoReg=x ALUsrc=1 Shift left 2 Add PCsrc=0 RegDst=x 1 1 1 0 0 0 0 1 Instr[15-0] Instr[25-21] Instr[20-16] Instr[15-11] Shift left 2 0 1 32 Instr[25-0] 26 PC+4[31-28] 28 Jump=0 ALUctr=add SignExt=sign The Single Cycle Datapath during Branch 15 • if (R[rs] - R[rt] == 0) then zero = 1; else zero = 0 beq rs, rt, Label op rs rt immediate 0 16 21 26 31 Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero RegWrite=0 Data Memory Address Write Data Read Data MemWrite=0 MemRead=x Sign Extend 16 32 MemtoReg=x ALUsrc=0 Shift left 2 Add PCsrc=1 RegDst=x 1 1 1 0 0 0 0 1 Instr[15-0] Instr[25-21] Instr[20-16] Instr[15-11] Shift left 2 0 1 32 Instr[25-0] 26 PC+4[31-28] 28 Jump=0 ALUctr=sub SignExt=sign Step 5: Adding control logic • Control logic is a component used to determine the value of control signals based on instruction type. • E.g. ALUctr, RegDst, …… 16 ALUctr RegDst ALUSrc ExtOp MemtoReg MemWr Zero Instruction<31:0>
<21:25>
<16:20>
<11:15>
<0:15>
imm16 Rd Rs Rt
PCsrc
Adr
Inst
Memory
DATA PATH
Control logic
Op
<21:25>
Fun
RegWr
Datapath after adding control logic: Control,
ALU control, and
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Why do we need two steps
(Control and ALU control) to
generate control signals for
the ALU?
ALU Control
• Controlling the ALU uses of multiple decoding levels
• main control unit generates the ALUOp bits
• ALU control unit generates ALUcontrol bits
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ALU Control Truth Table
• ALU’s operation based on instruction type and function
code.
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ALU Control Logic
• From the truth table can design the ALU Control logic
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Complete Datapath with Control Unit
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R-type Instruction Data/Control Flow
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Load Word Instruction Data/Control Flow
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Store Word Instruction Data/Control Flow
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Branch Instruction Data/Control Flow
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Main Control Unit
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Control Unit Logic
• From the truth table can design the Main Control logic
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Review: Handling Jump Operations
• Jump operation have to
• replace the lower 28 bits of the PC with the lower 26 bits of the
fetched instruction shifted left by 2 bits
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Adding the Jump Operation
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Main Control Unit of j
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Single Cycle Implementation Cycle Time
• Single Cycle Implementation Cycle Time approach is not
used because it is very slow.
• Clock cycle must have the same length for every
instruction.
• What is the longest path (slowest instruction)?
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Instruction Critical Paths
• Calculate cycle time assuming negligible delays (for
muxes, control unit, sign extend, PC access, shift left 2,
wires) except:
• Instruction and Data Memory (4 ns)
• ALU and adders (2 ns)
• Register File access (reads or writes) (1 ns)
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Single Cycle Disadvantages & Advantages
• Uses the clock cycle inefficiently – the clock cycle must
be timed to accommodate the slowest instruction.
• especially problematic for more complex instructions like floating
point multiply.
• May be wasteful of area since some functional units (e.g.,
adders) must be duplicated since they can not be shared
during a clock cycle.
• But it is simple and easy to understand.
33
Summary
• Single cycle datapath => CPI=1
• Long cycle time
• Cycle time for load is much longer than needed for all other
instructions
• 5 steps to design a processor
• 1. Analyze instruction set => datapath requirements
• 2. Select set of datapath components
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to determine
setting of control signals
• 5. Assemble the control logic
• Usually control is the hard part
• Complex control => long cycle time
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CO101�Principle of Computer Organization
Recap: A Single Cycle Datapath
The Big Picture: Where are We Now?
Step 4: Designing control signals
Adding the Control
(Almost) Complete Single Cycle Datapath
Meaning of the Control Signals
Steps in add instruction
The Single Cycle Datapath during add
The Single Cycle Datapath during sub??
The Single Cycle Datapath during addi
The Single Cycle Datapath during Load
The Single Cycle Datapath during Store??
The Single Cycle Datapath during Store
The Single Cycle Datapath during Branch
Step 5: Adding control logic
Datapath after adding control logic: Control, ALU control, and
ALU Control
ALU Control Truth Table
ALU Control Logic
Complete Datapath with Control Unit
R-type Instruction Data/Control Flow
Load Word Instruction Data/Control Flow
Store Word Instruction Data/Control Flow
Branch Instruction Data/Control Flow
Main Control Unit
Control Unit Logic
Review: Handling Jump Operations
Adding the Jump Operation
Main Control Unit of j
Single Cycle Implementation Cycle Time
Instruction Critical Paths
Single Cycle Disadvantages & Advantages
Summary