Carnegie Mellon
Speeding up Translation with a TLB
Page table entries (PTEs) are cached in L1 like any other memory word
PTEs may be evicted by other data references PTE hit still requires a small L1 delay
Solution: Translation Lookaside Buffer (TLB) Small hardware cache in MMU
Maps virtual page numbers to physical page numbers
Contains complete page table entries for small number of pages
1
Carnegie Mellon
TLB Hit
CPU Chip
2
PTE
3
CPU
1
VA
VPN
TLB
MMU
PA
Cache/ Memory
4
Data
5
A TLB hit eliminates a memory access
2
Carnegie Mellon
TLB Miss
CPU Chip
4
PTE
CPU
1
VA
2
VPN
TLB
MMU
3
PTEA
Cache/ Memory
PA
Data
6
5
A TLB miss incurs an additional memory access (the PTE)
Fortunately, TLB misses are rare. Why?
3