Exercise 4.13
In this exercise, we examine how data dependencies affect execution in the basic 5-stage pipeline
described in Section 4.5. Problems in this exercise refer to the following sequence of instructions:
Instruction Sequence
a. SW R16, -100(R6)
LW R4, 8(R16)
ADD R5, R4, R4
b. OR R1, R2, R3
OR R2, R1, R4
OR R1, R1, R2
4.13.1 [10] <4.5> Indicate dependences and their type.
4.13.2 [10] <4.5> Assume there is no forwarding in this pipelined processor. Indicate hazards and add
NOP instructions to eliminate them.
4.13.3 [10] <4.5> Assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate
them.
Exercise 4.13
In this exercise, we examine how data dependencies affect execution in the basic 5-stage pipeline
described in Section 4.5. Problems in this exercise refer to the following sequence of instructions:
Instruction Sequence
a. SW R16, -100(R6)
LW R4, 8(R16)
ADD R5, R4, R4
b. OR R1, R2, R3
OR R2, R1, R4
OR R1, R1, R2
4.13.1 [10] <4.5> Indicate dependences and their type.
a. LW may be a Read-After-Write dependency; if R6-100=R16+8, then both the SW and LW
instruction refer to the same memory address. ADD is also Read-After-Write dependency; the
ADD instruction needs the results of the LW instruction to perform its computation.
b. The second and third OR are RAW dependencies. The first and third OR instructions can also be a
Write-After-Write dependency; both the first and third instruction write to the same register
which can produce a hazard in OoO execution processors.
4.13.2 [10] <4.5> Assume there is no forwarding in this pipelined processor. Indicate hazards and add
NOP instructions to eliminate them.
a. SW, LW, NOP, NOP, ADD
b. OR, NOP, NOP, OR, NOP, NOP, OR
4.13.3 [10] <4.5> Assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate
them.
a. SW, LW, NOP, ADD
b. OR, OR, OR