CS 2506 Computer Organization II MIPS 3: Pipeline You may work in pairs for this assignment. If you choose to work with a partner, you may sign up to form a group on
Canvas under MIPS03 Homework Groups.
Prepare your answers to the following questions in plain text. Submit your file to Canvas by the posted deadline for this assignment. No late submissions will be accepted. For all questions, show supporting work if you want partial credit.
For questions 1 through 2, refer to the incomplete preliminary pipeline design, shown below, which includes the interstage buffers needed to synchronize signals and data with the instructions, but has no support for forwarding operands and hazard detection or stall. This datapath supports correct execution of any sequence of the following MIPS instructions: add, sub, and, or, slt, lw, sw and beq. This is true assuming that data and control hazards are handled by having the assembler insert nop instructions.
You may work with a partner on this assignment! 1
CS 2506 Computer Organization II MIPS 3: Pipeline
1. With the above incomplete pipeline design, the assembler should insert nop instructions to execute the sequence of instructions with data and/or control hazards correctly.
a)
b)
[8 points] Explain where and how many minimal nop instructions the assembler should insert in order to run the following sequence of instructions correctly.
add $t1, $t2, $t3 #1 sub $t1, $t1, $t4 #2 lw $t3, 0($t1) #3 sw $t1, 8($t5) #4 add $t2, $t1, $t2 #5
[8 points] Explain where and how many minimal nop instructions the assembler should insert in order to run the following sequence of instructions correctly.
add sub beq sw
L1: sw
$t1, $t2, $t3 #1 $t2, $t3, $t4 #2 $t2, $zero, L1 #3 $t4, 8($t5) #4 $t4, 16($t5) #5
2. [18 points] Suppose that a wrong implementation of the MIPS pipeline does not forward the Write register number through the ID/EX, EX/MEM, and MEM/WB interstage buffers. Instead, it directly feeds the output of the MUX controlled by RegDst as shown here:
Everything else in the pipeline is implemented as shown on the above diagram. For the sw instruction, the control signal RegDst is actually DC (don¡¯t care), but we will assume that it is set to 0 on this specific instance. Suppose that, initially, $t1=0x4000, $t2=0x1000, $t3=0x3000, and $t4=0x1000. Consider the execution of the following code in this buggy pipeline. Determine the final values of $t1, $t2, and $t3 after all the instructions leave the pipeline.
add $t1, $t2, $t3 sw $t2, 0x0000($t4) sw $t2, 0x1000($t4) add $t2, $t3, $t4 sw $t3, 0x2000($t4) sw $t3, 0x3000($t4) add $t3, $t2, $t4
#1
#2
#3
#4
#5
#6
#7
You may work with a partner on this assignment!
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CS 2506 Computer Organization II MIPS 3: Pipeline
For questions 3 through 6, refer to the pipeline design with forwarding and (load-use) hazard detection, shown below, which supports execution any sequence of the following MIPS instructions: add, sub, and, or, slt, lw, and sw. The datapath is simplified by omitting the sign-extended immediate and the logic for changing the PC to PC+4. Note that the datapath does not support branch or jump instructions.
3. [10 points] How many clock cycles would be required to execute the following sequence of instructions?
add $t1, $t2, $t3 #1
lw $t3, 0($t1) #2
lw $t2, 8($t1) #3
add $t2, $t2, $t3 #4
add $t3, $t1, $t2 #5
4. [18 points] Suppose that, due to a manufacturing defect, the control signal coming out of the HazardDetection unit and into the multiplexer labeledjin the figure suffers a stuck-at-0 error. That is, the control signal is always set to 0, which means that the multiplexer ignores its second input (which is hardwired to 0) and always forward the output of the Control Unit to the ID/EX interstage buffer. Assume that the rest of the hardware operates as designed.
Suppose that, initially, $t1=0x3000, $t2=0x2000, and $t3=0x1000 and that all words in memory are initialized to 0x2000. Consider the execution of the following code in this buggy pipeline. Determine the final values of the $t1, $t2, and $t3registers after all the instruction leave the pipeline.
add $t1, $t2, $t3 #1
lw $t3, 0($t1) #2
add $t2, $t2, $t3 #3
add $t3, $t1, $t2 #4
You may work with a partner on this assignment! 3
5.
[18 points] Depending on the existence and type of a data hazard, the Forwarding unit controls the two multiplexers which select the input to the ALU, labeledklin the figure. The control signals should be 00 when there is no data hazard; 10 on a hazard where we want to forward the data from the EX/MEM interstage buffer to the ALU; and 01 upon a hazard where we want to forward the data from the MEM/WB interstage buffer to the ALU.
Suppose that, due to a manufacturing defect, the Forwarding unit wrongly sets the control signals to be 00, when it should be 01. Assume that both multiplexers are vulnerable to this defect. Suppose that the Forwarding unit works correctly when the control signals should be 00 or 10. Assume that the rest of the hardware operates as intended.
Suppose that, initially, $t1=0x3000, $t2=0x2000, and $t3=0x1000 and that all words in memory are initialized to 0x2000. Consider the execution of the following code in this buggy pipeline. Determine the final values of the $t1, $t2, and $t3 after all the instructions leave the pipeline.
add $t1, $t2, $t3 #1
lw $t3, 0($t1) #2
add $t2, $t2, $t3 #3
add $t3, $t1, $t2 #4
[20 points] The Forwarding unit performs the following checks to detect a hazard in which data is forwarded from the MEM/WB interstage buffer (precisely speaking, from the multiplexer controlled by theMemtoRegsignal).
//Check for Register Rs (Check for Rt is similar)
//
6.
CS 2506 Computer Organization II MIPS 3: Pipeline
a) b) c) d)
if (MEM/WB.RegWrite //Condition #1
and (MEM/WB.RegisterRd != 0) //Condition #2
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd !=0) //Condition #3
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
and (MEM/WB.RegisterRd = ID/EX.RegisterRs)
[2 points] Why should the forwarding unit check condition #4? Be precise. [6 points] Why should the forwarding unit check condition #1? Be precise. [6 points] Why should the forwarding unit check condition #2? Be precise. [6 points] Why should the forwarding unit check condition #3? Be precise
//Condition #3 cont.
//Condition #4
You may work with a partner on this assignment!
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