Ex: 8.1 In the current source of Example 8.1 (Fig.8.1)wehaveIO =100μAandwewantto reduce the change in output current,
IO , corresponding to a 1-V change in output voltage,VO,to1%
W ⇒ L
2 = 15 × L2
120
= 200 × (0.2)2 = 15 ⇒ W2
TokeepVOV ofthematchedtransistorsthesame W
as that in Example 8.1, L of the transistor should remain the same. Therefore,
W 10μm
5μm= 1μm ⇒W=50μm
So the dimensions of the matched transistors Q1 andQ2 shouldbechangedto
W =50μmandL=5μm
Ex: 8.2 For the circuit of Fig. 8.4 we have
(W/L)2 (W/L)3 I2 =IREF(W/L) ,I3 =IREF(W/L)
W5 = 50 μm
W5 =4⇒W4 = 50μm =12.5μm
W4 4 Thus:
W1 =2.5μm,W2 =15μm,W3 =5μm W4 =12.5μm,andW5 =50μm
Ex: 8.3 From Eq. (8.21) we have ⎛ ⎞
⎜ m ⎟ V −V IO =IREF⎜⎝ ⎟⎠ 1+ O BE
Exercise 8–1
of IO.
W2 W2
W2 =15μm, W =6⇒W1 = 6 =2.5μm
1
W3 =2⇒W3 =2×W1 =5μm OrOr W1
Thatis,I = VO =0.01I ⇒ 1V
= 0.01 × 100 μA
ro2 = 1V =1M
To allow the voltage at the drain of Q5 to go up to within 0.2 V of positive supply, we need
VOV5 =0.2V:
o2
o2
1μA V′×L
1 W I= k′ V2
20×L ro2= I ⇒1M=100μA
O
100V ⇒L=20V/μm=5μm
5 2p L OV5
A
5 1μAW 2
80μA=280 V2
(0.2) ⇒ =50⇒W5 =50L5
W
L 5
L
= 2×80 80×(0.2)2
5
11 1+m+1VA2
and I = I (W/L)5
β
5 4(W/L)
⎛ ⎞
4
Since all channel lengths are equal, that is,
1 1+1+1
100
⎟⎠
1 + 5 − 0.7 100
L =L =···=L =1μm
IO = 1 mA⎜⎝
= 1.02 mA
IO =1.02mA
VA Ro =ro2 = I
12 5 and
IREF =10μA, I2 =60μA, I3 =20μA, I4 = I3 =20μA, andI5 =80μA,
10
100V
= 1.02mA =98k≃100k
we have
I=I W2⇒W2=I2 =60=6
Ex: 8.4
O
VCC
2 REF W1 W1 IREF I = I W3 ⇒ W3 = I3
= 20 = 2 10
IREF
From Eq. (8.23), we have
IO
Q2
3 REF W1 W1 IREF
I = I W5 ⇒ W5 = I5 = 80 = 4
R
5 4W4 W4 I4 20
To allow the voltage at the drain of Q2 to go down to within 0.2 V of the negative supply voltage, we needVOV2 =0.2V:
1W1W I=μCV2=k′V2
Q1
VO
2 2 n ox L OV 2 2 n L 22
OV 2
1 μAW 60μA= 200 2
2VL2
(0.2)2
I V−V IO= REF 1+ O BE
1+(2/β) VA
whereVBE=VTln O
IS
⇒
L1 To obtain
=12.5
I W
Exercise 8–2
= 0.025 ln
0.5 mA =
0.5 × 10−3 10−15
I
= 0.673 V
REF 1+(2/100)
1 + =0.497mA
⇒
(W/L)2
⇒ = 5 × 12.5 = 62.5
2−0.673 50
Ais =5
5=Ais = (W/L)1
IREF =0.5mA 1.02
W L 2
1.026 mA
IREF = VCC −VBE ⇒R= VCC −VBE
R IREF
Ro = ro2 = VA2 = VA2 ID2 5ID1
R =
Thus,
40k= VA2
5 − 0.673
= 8.71 k VOmin =VCEsat =0.3V
0.497 mA
ForVO =5V,FromEq.(8.23)wehave
I V−V IO=REF 1+O BE
5×0.1 ⇒VA2=20V
1 + (2/β) VA
0.497 5−0.673V
But
VA2 =V′ L2
IO=1+(2/100) 1+ 50
=0.53mA
A2
20 = 20×L2
Ex:8.5 I1 =I2 =···=IN = IC|QREF At the input node,
⇒L2 =1μm Selecting L1 = L2, then L1 =L2 =1μm
W1 = 12.5 μm
W2 = 62.5 μm
Ex: 8.7
Using Eq. (8.42):
IREF = IC|QREF + IB|QREF +IB1 +···+IBN =IC|QREF +(N+1)IB|QREF
(N + 1)
= IC|QREF + β IC|QREF
IREF
N+1 β
⇒ IC|QREF =
1+
Thus,
I1=I2=···=IN= REF Q.E.D
I
1+N+1 β
g=2μCW·I m noxLD
ForID =10μA,wehave
gm = 2(387 μA/V2)(10)(10 μA)
=0.28mA/V
Using Eq. (8.46):
′ 2μn Cox (W/L) A0 = VA √ID
For β = 100, to limit the error to 10%, N+1 N+1
0.1= β = 100 ⇒N=9
Ex: 8.6
Rin≃1 22
gm1
Now, Rin = 1 k, thus
gm1 = 1 mA/V
5 V/μm 2(387 μA/V )(10)(0.36) √10 μA
=
A0 = 50 V/V
1 ID and A0 with √I ,
But gm1 =
Since gm varies with
W D
2(μnCox) W
ID1
for
ID =100μA⇒gm =0.28mA/V 10 =0.88mA/V
L 1
1001/2
1= 2×0.4× L ×0.1 1
10 1/2
A0 =50 100 =15.8V/V
IC1 = I = 100 μA = 0.1 mA
gm1 = IC1 = 0.1mA =4mA/V
VT 25mV
β1 100
Rin =rπ1 = g = 4mA/V =25k
Exercise 8–3
ForID =1mA,wehave
1 1/2
gm =0.28mA/V
0.010
=2.8mA/V
m 1
r =VA = 50V =500k
A0 = 50 Ex: 8.8
1
= 5 V/V
VDD
vI
o1 I 0.1 mA
ro2 = |VA| = 50V =500k
0.0101/2
Q3 IREF
Q2
Q1
vO
I 0.1 mA
A0 = gm1 ro1 = (4 mA/V)(500 k) = 2000V/V
Av = −gm1 (ro1 ∥ro2) = −(4 mA/V)× (500 k ∥ 500 k) = −1000 V/V
Ex: 8.10 Refer to Fig. 8.18(b), vo =iRL
vsig =i(Rs +Rin)
Thus,
Since all transistors have the same
W=7.2μm, L 0.36μm
we have
IREF =ID3 =ID2 =ID1 =100μA W
vo= RL vsig Rs +Rin
Q.E.D
gm1 = 2μnCox L
Ex:8.11 Sincegmro ≫1,weuseEq.(8.54), R ≃ 1 + RL
ID1 = 2387 μA/V2 7.2
in gm gmro
1
RL
0
ro
(gm ro )ro
∞
Rin
1
gm
2
gm
ro
∞
= 1.24 mA/V V′ L
5V/μm(0.36μm) 0.1 mA
0.36
(100 μA)
ro1= An 1= ID1
=18k
Ex: 8.12 For gmro ≫ 1, we use Eq. (8.58), Rout ≃ro +(gmro)Rs
to obtain
Ex: 8.13 Avo remains unchanged at gmro. With a load resistance RL connected,
A =A RL
v vo RL+Ro
= (gmro) RL
RL + (1 + gmRs)ro
Ex: 8.14 Use Eq. (8.63) R≃r ro+RL
in e RL ro + β + 1
ro2 = Ap ID2
2 =
=21.6k
|V ′ |L
6 V/μm (0.36 μm) 0.1 mA
Voltage gain is
Av =−gm1(ro1∥ro2)
Av =−(1.24mA/V)(18k∥21.6k) = −12.2 V/V
Rs
0
ro
(gm ro )ro
∞
Rout
ro
(gm ro )ro
(gmro)2ro
∞
Ex: 8.9
VBIAS
vi Rin
VCC
I
vo
Q
Q1
2
to obtain
Ex: 8.19
VG4 1.1 V
Exercise 8–4
RL
0
ro
(β + 1)ro
∞
Rin
re
2 re
1
2rπ
rπ
VDD 1.8 V Q4
Ex: 8.15 Using Eq. (8.68), Rout ≃ro+(gmro)(Re∥rπ) we obtain
Ex:8.16 Ro =[1+gm(Re ∥rπ)]ro where
gm = 40 mA/V, rπ = β = 2.5 k, gm
Re =0.5k, andro = VA = 10 =10k
VG3 0.8 V
Q3
VG2 1.0 V
vO Q2
Re
0
re
rπ
ro
∞
Rout
ro
2 ro
β 2+1 ro
(β + 1)ro
(β + 1)ro
IC
Thus,
Ro =[1+40(0.5∥2.5)]×10 =177k
Without emitter degeneration, Ro =ro =10k
1
Q1 VI 0.7 V
If all transistors are matched and are obviously operating at the same ID, then all |VOV | will be equalandequaltothatofQ1,namely,
|VOV | = 0.7 − 0.5 = 0.2 V
VD1 = VS2 = VG2 −Vtn −VOV =1.0−0.5−0.2=0.3V
ThelowestvDS2 cangois|VOV|=0.2V
∴ vOmin = VDS1 + VDS2 = 0.3 + 0.2 = 0.5 V Similarly,VSG4 =VSG3 =0.7V
VD4 =VS3 =VG3 +|Vt|+|VOV|
= 0.8 + 0.5 + 0.2 = 1.5 V
vSD3 cangoaslowas|VOV|,so
vOmax =VD4 −vSD3min =1.5−0.2=1.3V
Ex: 8.17 Since the CG transistor Q2 increases the output resistance by a factor approximately equal to gm2ro2,
K ≃gm2ro2
Ex:8.18 IfLishalved L=
0.55 μm 2
|VA|=VA′·L,weobtain
Ex: 8.20 Refer to Fig. 8.33.
2ID 2×0.2
and
(0.3V) (100μA) W V
gm1 =gm2 =gm3 =gm4 = |VOV| = 0.2 = 2 mA/V
0.55 μm |VA|=5V/μm 2
ro1 =ro2 =ro3 =ro4 = |VA| = 2 =10k ID 0.2
Ron =(gm2ro2)ro1 =(2×10)×10=200k Rop =(gm3ro3)ro4 =(2×10)×10=200k Ro =Ron∥Rop =200∥200=100k
Av =−gm1Ro =−2×100=−200V/V
=1.375V Ro = |VA| ·|VA|= 2(1.375 V)2
|VOV|/2 ID = 126 k
1 SinceID = μpCox
2
L
|VOV|2 1+ SD |VA|
W
L =
2 (100 μA)
0.3 V 1.375 V
Ex: 8.21 g
= g m1 m2
= g m
90μA/V2 (0.3V)2
1+ L2
0.1 mA (0.2/2) V
W
ID =V =
=1mA/V
= 20.3
OV
ro1 =ro2 =ro
=VA= 2V =20k
R +r Rin2 = L o2
(a) ID1 =I andID2 =I
Since VOV1 = VOV2 = 0.2 V, we have
ID 0.1 mA
so,g r =1mA/V(20k)=20
1 W μC V2
Exercise 8–5
mo
(a) ForRL =20k,
ID2 2pox L OV2 I I=1 W2 =I=1
=
∴ Av1 = −gm1 (ro1 ∥ Rin2)
= 1.9 k
1
20k+20k 1 + 20
D1 μC V2
2 n ox L OV1
1 + gm2ro2
= −1 mA/V (20 ∥ 1.9) = −1.74 V/V
Thus,
k′W pL2 Wk′nW W=1⇒L=k′L
k′2p1 or nL1
If we use the approximation of Eq. (8.83),
Rin2≈ RL + 1 =20k+ 1 =2k
k′W =n
gm2ro2 gm2 20 1 mA/V then
k′n L1 4
Av1 = −1 mA/V(20 k∥2 k) = −1.82 V/V Continuing, from Eq. (8.80),
Av =−gm1[(gm2ro2ro1)∥RL]
Av = −1 mA/V {[(20) (20 k)] ∥ 20 k}
= −19.0 V/V
Av −19.0
Av2 = A = −1.82 =10.5V/V
v1
(b) Now, for RL = 400 k,
Rin2≃RL +1=400k+ 1 gm2ro2 gm2 20 1 mA/V
= 21k
Av1 = −1 mA/V(20 k∥21 k) = −10.2 V/V
Av =−1mA/V[(20)(20k)]∥400k
= −200 V/V
Av −200
Av2 = A = −10.2 =19.6V/V
W W or =4
L2 L1
(b) The minimum voltage required across current source I1 would be |VOV | = 0.2 V, since it is made with a single transistor. If a 0.1-VPP signal swing is to be allowed at the drain of Q1, the highest dc bias voltage would be
VDD −|VOV|−0.1Vpp =1.8−0.2−1(0.1) 2 2
= 1.55 V
(c)VSG2 =|VOV|+ Vtp =0.2+0.5=0.7V VG2 canbesetat1.55–0.7=0.85V.
(d) Since current source I2 is implemented with a cascoded current source, the minimum voltage required across it for proper operation is
2VOV = 2(0.2 V) = 0.4 V.
(e) From parts (c) and (d), the allowable range of signal swing at the output is from 0.4 V to 1.55 V –VOV or1.35V.
Ex: 8.22
vi
VDD 1.8 V I1 2I
Q1 Q2
Ex: 8.23 Referring to Fig. 8.38, Rop =(gm3ro3)(ro4∥rπ3) and Ron = (gm2ro2) (ro1 ∥ rπ2)
The maximum values of these resistances are obtained when ro ≫ rπ and are given by
Ron = (gm2ro2) rπ2
2
Ron = β2ro2
max
Rop = β3ro3 max
so,0.4V≤v ≤1.35V. v1O
VG2
max
R =(gr)r
vo II
op max m3 o3 π3 Since gmrπ = β,
SinceA =−g R ∥R , v m1 on op
|Avmax| = gm1 β2ro2 ∥β3ro3
Ex: 8.24 For the npn transistors,
gm1 =gm2 = |IC| = 0.2mA =8mA/V |VT | 25 mV
β 100
rπ1 =rπ2 = g = 8mA/V =12.5k
1 3.6 × 387 ×
2
Exercise 8–6
100 =
× VOV
m
ro1=ro2=|VA|= 5V =25k
VGS =0.227+0.5=0.727V VOmin = VG3 − Vt3
=VGS4 +VGS1 −Vt3 Thus,
VOmin =2VGS −Vt
=Vt+2VOV
= 0.5 + 2 × 0.227 = 0.95 V
2 ID 2 × 0.1
gm=V = 0.227 =0.88mA/V
OV
ro = VA = VA′L = 5×0.36 =18k
ID ID 0.1
Ro = (gm3ro3)ro2 = (0.88 × 18) × 18
= 285 k
Ex: 8.26 For the Wilson mirror from Eq. (8.94),
2 0.36 ⇒VOV =0.227V
|IC | 0.2 mA From Fig. 8.38,
R =(g r )(r ∥r ) on m2 o2 o1 π2
=(8mA/V)(25k)(25k∥12.5k) Ron = 1.67 M
For the pnp transistors,
gm3 =gm4 = |IC| = 0.2mA =8mA/V
25 mV
50 =6.25k
r =r =|VA|= 4V =20k IREF o3 o4 |IC| 0.2 mA
VT
rπ3 =rπ4 = β = gm
wehave
8 mA/V IO ≃ 1 = 0.9998
1+2 β2
Rop = (gm3ro3) (ro4 ∥ rπ3)
= (8 mA/V) (20 k) (20 k ∥ 6.25 k)
Rop = 762 k
A =−g R ∥R v m1 on op
= −(8 mA/V) (1.67 M∥762 k)
Av = −4186 V/V
A occurswhenr andr are≫r . vmax o1 o4 π
Then
Ron =(gm2ro2)rπ2 =β2ro2
Ron = 100(25 k) = 2.5 M
Rop = (gm3ro3) rπ3 = β3ro3
Rop =50(20k)=1M
Finally,
Avmax = −(8 mA/V)(2.5 M∥1.0 M) Avmax =−5714V/V
Ex: 8.25 Refer to the circuit in Fig. 8.39. All transistors are operating at ID = IREF = 100 μA and equal VOV , found from
Thus |IO − IREF| × 100 = 0.02% IREF
whereas for the simple mirror from Eq. (8.18) we have
IO IREF
1
= =0.98
1 + 2 β
|IO − IREF|
I ×100=2%
REF
Hence
For the Wilson current mirror, we have
Ro = βro = 100×100k =5M 22
and for the simple mirror, Ro = ro = 100 k.
Ex: 8.27 For the two current sources designed in Example 8.6, we have
IC
gm = =
10 μA 25mV
mA V
= 0.4
ro = VA = 100V =10M,
VT
IC 10 μA
1 W
β
rn = g = 250 k
m
For the current source in Fig. 8.43(b), we have
R =r =r =10M o o2 o
I = μC V2 D 2 n ox L OV
For the current source in Fig. 8.43, from Eq. (8.102), we have
Rout ≃[1+gm(RE∥rn)]ro
From Example 8.6, RE = R3 = 11.5 k; therefore,
mA
Rout ≃ 1+0.4 V (11.5k∥250k) 10M
∴Rout =54M Ex: 8.28
Gv ≡ vo = −145.5 V/V vsig
These results apply for both Rsig = 4 k and Rsig = 400 k. If in the CC–CE amplifier of Example 8.7, Rsig = 400 k, Gv becomes
Exercise 8–7
2 × 0.2
0.2
gmb =χgm =0.2×2=0.4mA/V
ro1=ro3=VA=5=25k ID 0.2
RL =ro1∥ro3∥ 1 =25∥25∥2.5k gmb
×0.99×−160
Q1
2ID gm = V
=
= 2 mA/V
Gv = 255 255 + 400
= −61.7 V/V Ex: 8.30
Rsig
vsig
(b2 1) (re2 RE) From the figure we can write
OV
re1
Q2
= 2.083 k
vo = RL = 2.083
vi RL+ 1 2.083+1 gm 2
Ex: 8.29
= 0.81 V/V
Rin
RE
vo
Rout
Rin =(β1 +1)[re1 +(β2 +1)(re2 +RE)] bi
Rsig
b viQ vo
Rout=RE∥ re2+re1+Rsig/(β1+1) β2+1
1
ib
vo =
RE
re1 + Rsig/(β1 + 1)
vsig v1 QR RE+re2+
0
sig gm1 2
L
β2+1
ForIE2 =5mA,β1 =β2 =100,RE =1k,and
Rsig = 100 k, we obtain re2 = 25 mV = 5
rp2 55
gm1 = √
5 mA
IE1 = = ≃0.05mA
0.05 mA
Rin =101×(0.5+101×1.005)=10.3M
2knID = 2×8×1
β2 + 1 101
re1 = 25mV =500
= 4 mA/V
1 = 0.25 k
gm1
gm2 =40mA/V
rπ2=100=2.5k 40
Rout =1∥ 0.005+
0.5 + (100/101)
101 ≃20
vo = vsig
1
1 + 0.005 + 0.5 + (100/101)
101
Rin = ∞
ib = vi
=
vsig 1 +r
=
vsig 0.25+2.5
=0.98V/V
Ex: 8.31 Refer to Fig. 8.49.
re = 25
Rin =(β1 +1)(2re)=101×0.05=5.05k
1 +r
g π2 g π2
m1 m1 2.75
= sig
v
vo =−βib RL =−100×4vsig 2.75
vo = α2RL ≃ 5 =100V/V vi 2 re 0.05
vo =vi ×vo
and
vo=iRL Thus,
vo =1gmRL vi 2
where
2ID 2I gm=V =V
OV OV
Thus,
vsig vsig
vi ×vo
vi
=
Rin
Rin +Rsig
Exercise 8–8
5.05
= 5.05+5 ×100=50V/V
Ex: 8.32
vo = 1 × 2I RL = IRL vi2VOV VOV
Q.E.D
RL
(b) I =0.1mAandRL =20k,toobtainagain of 10 V/V,
10= 0.1×20 VOV
The required W/L can be obtained from D 2n L OV
1 W
0.1 = × 0.2 × × 0.04
2L
⇒ W = 25 L
i
Q2 111W
vo
vi Q1
gm1 i gm2 I=k′ V2
⇒VOV =0.2V
(a) From the figure we see that
i=vi =1gmvi 2/gm 2
8.1 Referring to Fig. 8.1, VDD = 1.3 V,
IO =IREF =100μA,L=0.5μm,W =5μm,
8.3 VDD VDD
Q1 Q2
Chapter 8–1
VA′ =5V/μm,Vt =0.4V,k′n =500μA/V2 1 W
I =I = k′ V2 O D 2n L OV
VO
2ID IR
VOV = W k′n L
2 (100 μA) =500μA/V2 5 =0.2V
0.5
VDS =VGS =Vt +VOV =0.4+0.2=0.6V
REF
Set |VOV | = VDD − VOmax
= 1.3−1.1 = 0.2 V
V =V −V −|V | G DD tp OV
= 1.3−0.4−0.2 = 0.7 V R= VG = 0.7V =8.75k
IO
R= VDD −VGS = 1.8−0.6 =12k IREF 0.1 mA
The lowest VO will be VDS2 =VOV =0.2V
VA′L RO=ro=I =
ID1 80 μA
5V/μm×0.5μm 100μA
=25k
1
ID = 2μpCox
W
L |VOV|2
D
I ≈VO =0.5V=20μA
thus
W= 2ID
= 2×80μA
80 μA/V2 × 0.22
D ro 25 K 8.2 Refer to Fig. 8.1.
=50 8.4 Referring to Fig. 8.2, if W2 = 5 W1 and we
(W/L)2
IO =ID2 =IREF(W/L) =20μA×5=100μA
1
VOmin =VOV =0.2V FromEq.(8.8):
△IO
I = 10%
O
△IO =0.1×150=15μA
L μpCox|VOV |2
let L1 = L2, then we obtain
△VO = 1.8−0.3 = 1.5 V
r = △VO = 1.5V =100k
(W/L) V−V 2·IREF 1+O GS
o △IO 15μA But
IO=
VGS =Vt +VOV =0.5V+0.2V=0.7V
r o = V A = V A′ L IO IO
10 × L
100= 0.15 ⇒L=1.5μm
⇒VA =15V
VOV =VDS2min =0.3V
VGS =Vt +VOV =0.5+0.3=0.8V 1 W V
I = k′ V2 1+ DS D2nLOV VA
1 W 0.8 150= 2 ×400× L ×0.09 1+ 15
W
⇒ L =7.91
W =7.91×1.5=11.9μm
R= VDD −VGS = 1.8−0.8 =6.7k IREF 0.15
(W/L)1 VA2
Thus, ID equal 5IREF will be obtained at
VO =VGS =0.7V
ForVO =VGS +1=1.7V
1.7−0.7
IO =100 1+ 20 =105μA
The corresponding increase in IO , IO is, thus, 5μA.
8.5 ReferringtoFig.P8.5,weobtain
VGS1 = VGS2 so that ID2 = (W/L)2 and ID1 (W/L)1
I =I (W/L)2 D2 REF (W/L)1
ID3 = ID2
VGS3 = VGS4, thus
=
ID4 = 40 =
1
2 L
V2 OV
(W/L)2 (W/L)4 IO = ID4 = IREF (W/L) . (W/L)
W
ID4
ID3
(W/L)4 (W/L)3
W
Chapter 8–2
1 132L4
μnCox
×400× ×0.22
4
8.6 Refer to the circuit of Fig. P8.6. For Q2 to operate properly (i.e., in the saturation mode) for drain voltages as high as +0.8 V, and provided its width is the minimum possible, we use
|VOV|=0.2V
Note that all three transistors Q1, Q2, and Q3 will be operated at this value of overdrive voltage. For Q1,
W ⇒=5
L 4
W4 = 2.5 μm
Finally, since
I5 =80μA=2I4,
W W L = 2 L
W
⇒ L = 10
I =1μC W |V |2 D1 2 p ox L OV
1 20=1×100× W ×0.04
2L1 W
W5=5μm
TofindthevalueofR,weuse
|VSG1|=|Vtp|+|VOV1|
= 0.5 + 0.2 = 0.7 V
54
ID1 = IREF = 20 μA 5
⇒ L = 10 1R==
1 − |VSG1| IREF
For L = 0.5 μm,
W1 = 5 μm
Now,for
I2 =100μA=5IREF,wehave (W/L)2 = 5
(W/L)1 W
0.3 V 0.02 mA
= 15 k
The output resistance of the current source Q2 is
|V | |V′ |×L ro2 = A2 = Ap
I2 = 5×0.5 =25k
0.1 mA
The output resistance of the current sink Q5 is
I2
⇒ = 5 × 10 = 50
L2 VV′×L
W =50×0.5=25μm 2
For
I3 = 40 μA = 2IREF, we obtain
(W/L)3 = 2 (W/L)1
W ⇒ L
ro5 = A5 = An I5 I5
= 20 W3 = 10 μm
= 5×0.5 = 31.25 k 80
8.7 Referring to the figure, suppose that Q1 has W =10μm,Q2 hasW =20μm,andQ3 has W = 40 μm.
3
We next consider Q4 and Q5. For Q5 to operate in saturation with the drain voltage as low as
−0.8 V, and for it to have the minimum possible W/L, we operate Q5 at
VOV =0.2V
This is the same overdrive voltage at which Q4
will be operating. Thus, we can write for Q4, I4 =I3 =40μA
and using
Q1
Q3 I2 I3
VDD
Q2
I1 IREF
(1) With Q1 diode connected,
(W/L) 2 REF (W/L)1
I1 =100μA 20 =50μA 40
10
I1 =100μA 40 =25μA
For the six cases above we obtain
(1) W =W1 =10μm⇒VSG =1.05V
(2) W =W2 =20μm⇒VSG =0.92V
(3) W =W3 =40μm⇒VSG =0.82V
(4) W =W1 +W2 =30μm⇒VSG =0.86V (5) W =W2 +W3 =60μm⇒VSG =0.78V (6) W =W1 +W3 =50μm⇒VSG =0.80V
8.8 (a) If IS = 10−17 A and we ignore base currents, then
2 =100μA 40
20 10
=200μA
I =I
I3 =100μA 10 =400μA
Chapter 8–3
(2) WithQ2 diodeconnected,andW =20μm, 10
I3 =100μA 20 =200μA
(3) If Q3 with W = 40 μm is diode connected,
IREF = IS eVBE /VT so that 20
I2 =100μA 40 =50μA
So, with only one transistor diode connected, we can get 25 μA, 50 μA, 200 μA, and 400 μA, or four different currents.
Now, if two transistors are diode connected, the effective width is the sum of the two widths.
(4) If Q1 and Q2 are diode connected, then Weff =20+10=30μm,sothat
40
I3 =100μA 30 =133μA
(5) If Q2 and Q3 are diode connected, then Weff =20+40=60μm,sothat
10
I1 =100μA 60 =16.7μA
(6) If Q1 and Q3 are diode connected, Weff =10+40=50μm,sothat
20 I2=100μA 50 =40μA
So three different currents are obtained with double-diode connects.
To find V , we use the following for the SG
diode-connected transistor(s): 1 W
VBE = VT ln IREF 10−17
For IREF = 10 μA,
10−5
VBE = 0.025 ln 10−17 For IREF = 10 mA,
10−2 VBE = 0.025 ln 10−17
= 0.691 V
= 0.863 V
So for the range of 10μA≤IREF ≤10mA, 0.691 V ≤ VBE ≤ 0.863 V (b) Accounting for finite β,
1
IO = IREF · 1 + 2/β
For IREF = 10 μA,
IO = 10μA =9.62μA
For IREF = 0.1 mA,
IO = 0.1mA =0.098mA
ForIREF =1mA,
IO = 1mA =0.98mA
1+2 50
1+2 100
ID = 2μpCox L (VSG −|Vtp|)2
and substitute I = I = 100 μA. Thus
1+2 100
D REF
1 W
100=
⇒VSG =0.6+
1μm 2
ForIREF =10mA, 10 mA
2
×100×
(VSG −0.6)2
W(μm) 1+
IO= 2 =9.62mA 50
8.9
8.11 Nominally, IO = IREF = 1 mA ro2 = VA2 = 90 = 90 k
Chapter 8–4
IO 1
ro2 = VO ⇒ 10−1 =90⇒IO =0.1mA
IO IO
IO = 0.1 = 10% change
I =mI
O C1
IO 1
8.12 Equation (8.21) gives the current transfer
ratio of an npn mirror with a nominal ratio of m:
mV−V 1+O BE
IO=IREF
I+I β
A node equation at the collector of Q1 yields
1 + m + 1 VA2
IREF = IC1 + O
Substituting IC1 = IO/m results in
This equation can be adapted for the pnp mirror of Fig. P8.12 by substituting m = 1, replacing VO with the voltage across Q3, namely (3 − VO), replacing VBE with VEB, and VA2 with |VA|:
1+[(3−VO −VEB)/|VA|]
IO =IREF 1+(2/β) (1)
Now,substitutingIO =1mA,VO =1V,β=50, |VA| = 50 V, and
IS 10−15
results in
IREF 1.013
Maximum allowed voltage VO = 3 − 0.3 = 2.7
V. For VO = 2.7 V, Eq. (1) yields
C1
β
IO = m IREF 1+ m+1
β
Q.E.D.
For β = 80 and the error in the current transfer ratio to be limited to 10%, that is,
m
m+1 ≥0.9m
−3 VEB =VT lnIO =0.025ln 10
1+β
m + 1 1
=0.691V 1×(1+0.04) = 1.013 mA
1+ β ≤0.9 m + 1 1
IREF =
R=VCC−VEB =3−0.691=2.28k
β ≤0.9−1
1 + 3 − 1 − 0.691 50
m≤β1−1−1 0.9
1 m ≤ 80 0.9 −1
−1 = 7.88
Thus, the largest current transfer ratio possible
1+
3−2.7−0.691
50 = 0.966 mA
IO = 1.013
is 7.88.
8.10
1.04
For VO = −5 V, Eq. (1) yields
1+ 3−(−5)−0.691
IO = 1.013 50 = 1.116 mA
1.04
Thus, the change in IO is 0.15 mA.
8.13 The solution is given in the circuit diagram. Note that the starting point is calculating the current I in the Q1–R1–Q2 branch. See figure on next page.
8.14 Refer to the circuit in Fig. P8.14. V2 =2.7−VEB =2.7−0.7=+2V V3 =0+VEB =+0.7V
Thus, Q3 and Q4 are operating in the active mode, and each is carrying a collector current of I/2. The same current is flowing in Q2 and Q1; thus
VV
Q1
IREF
For identical transistors, the transfer ratio is
IO = 1 = 1 =0.96 IREF 1+2/β 1+ 2
50
DD
DD
Q2 IO
This figure belongs to Problem 8.13.
Chapter 8–5
V1 = −2.7 + I R 2
But
V1 = −VBE1 = −0.7
Thus,
−0.7 = −2.7 + 1IR 2
⇒ IR = 4 V
The current I splits equally between Q5 and Q6;
thus
I
V4 =−2.7+ 2 R=−2.7+2=−0.7V
I R
V5 =−2.7+ 2 2 =−2.7+1=−1.7V
Thus, Q5 and Q6 are operating in the active mode as we have implicitly assumed.
Note that the values of V1, V2, V3, V4, and V5 do not depend on the value of R. Only I depends on the value of R:
(a) R=10k ⇒ I= 4 =0.4mA 10
(b) R=100k ⇒ I = 4 =0.04mA 100
8.15 There are various ways this design could be achieved, but the most straightforward is the one shown:
Q1 1
Q2 1
R 0.2 mA 0.4 mA
0.8 mA
2 mA
20
2 4 8
0.5 mA 5
1 mA 10
With this scheme,
R= 5−0.7−0.7−(−5) =86k
0.1 mA
and each transistor has EBJ areas proportional to the current required. Multiple, parallel transistors are acceptable.
Note: This large value of R is not desirable in integrated form; other designs may be move suitable.
Even without knowing exact circuitry, we can find the total power dissipation as approximately
PT =PCC +PEE
PT =5V(0.1+0.2+0.4+0.8) mA +5 V(0.1+0.5+1+2) mA
PT =7.5mW+18mW=25.5mW
8.16 (a)
Figure2showsthespecialcaseofV =0V.As before, the voltage at X, VX , will be equal to V . Thus
VX =0
That is, a virtual ground appears at X, and thus
Chapter 8–6
the current I that flows into X can be found from I=5−VX =5−0=0.5mA
10 k 10
This is the current that will be mirrored to the
output, resulting in IZ = 0.5 mA.
8.17 Using Eq. (8.28), Rin = ro1 ∥ 1
gm1 where
ro1 = VA = VA′L = 10×0.5 =50k ID1 ID1 0.1 mA
W 2μnCox L
10 0.5
Figure 1
Figure 1 shows the current conveyor circuit with Y connected to a voltage V , X fed with a current source I, and Z connected to a voltage VZ that keeps Q5 operating in the active mode. Assuming that all transistors are operating in the active mode and that β ≫ 1, so that we can neglect all base currents, we see that the current I through Q1 will flow through the two-output mirror Q3, Q4, and Q5. The current I in Q5 will be drawn from Q2, which forms a mirror with Q1. Thus
VEB2 = VEB1 and the voltage that appears at X will beequaltoV.ThecurrentinQ5 willbeequalto I, thus terminal Z sinks a constant current I.
gm1 =
=
1 = 0.71 k
gm1 Thus,
ID1
×0.1 = 1.414 mA/V
2×0.5×
1
Rin =50∥0.71=0.7k=700 Ais = (W/L)2 = 50/0.5 = 5 A/A
(W/L)1
VA RO =ro2 = I
5×0.1
10/0.5 VA′ L
= I D2
(b)
D2
= 10×0.5 =10k
8.18 Ais = 4 = (W/L)2 (W/L)1
Since L1 = L2, then W2 =4
W1
Rin = ro1 ∥ 1 ≃ 1
gm1 gm1
Rin =500⇒gm1 =2mA/V
For
Figure 2
W gm1 = 2μnCox L
ID1
1
Thus, v = i R = g v W3 R o d3L m1iWL
W 2
Chapter 8–7
2 = 2 × 0.4 × W
⇒ L =25 1
L
× 0.2
Thus, the small-signal voltage gain will be vo = gm1RL (W3/W2)
vi
8.20 Replacing Q1 and Q2 with their small-signal hybrid-π models results in the equivalent circuit shown in the figure below. Observe that the controlled source gm1vπ1 appears across its controlling voltage vπ1; thus the controlled source can be replaced with a resistance (1/gm1). The input resistance Rin can now be obtained by inspection as
Rin=ro1∥ 1 ∥rπ1∥rπ2 gm1
Since ro1 ≫ rπ1,
Rin≃ 1 ∥rπ1∥rπ2 (1)
gm1
The short-circuit output current io is given by
io = gm2vπ2
Since vπ2 = vπ1 = iiRin, then the short-circuit
current gain Ais is given by Ais=io =gm2Rin
ii
1
=gm2 g ∥rπ1∥rπ2 (2)
m1
For situations where β1 and β2 are large, we can
neglect rπ1 and rπ2 in Eqs. (1) and (2) to obtain Rin ≃1/gm1
Ais ≃ gm1/gm2
1
R = r = V A = V A′ L O o2 ID2 ID2
Thus,
20= 20L
4×0.2 ⇒ L = 0.8 μm
W1 =25×0.8=20μm W2 =4W1 =80μm
8.19 Refer to Fig. P8.19. Consider first the diode-connected transistor Q2. From the figure we
g2
vgs2
S2
d2
gm2vgs2
g2, d2
S3
g1 m2
see that from a small-signal point of view it is equivalent to a resistance 1/gm2. Thus the voltage gain of Q1 will be
vd1 =−gm1× 1 =−gm1 vi gm2 gm2
The signal current in the drain of Q1, gm1 vi, will be mirror in the drain of Q3;
i =g v(W/L)3 =g vW3 d3 m1 i(W/L) m1 iW
22
which flows through RL and produces the output
voltage vo,
This figure belongs to Problem 8.20.
C1
ro1
B1, B2
C2
io ro2
Ro
ii
Rin
vp1 gm1vp1
rp1
rp2 vp2
gm2vp2
8.21 (a)
g d g,d 0.1
Chapter 8–8
IC3 ≃ IB1 + IB2 = 2 IB1 = 2 × IC1 β
vgs
s
gmvgs
Figure 1
g1 m
= 2 × 100 = 0.002 mA
1mA
= 0.6 V
s
VBE3 = 0.7 − 0.025 ln 0.002 mA = 0.545 V
Replacing the MOSFET with its hybrid-π model but neglecting ro results in the equivalent circuit in Fig. 1. Observing that the controlled-source gmvgs appears across its control voltage vgs, we can replace it by a resistance 1/gm, as indicated. Thus the small-signal resistance of the diode-connected MOS transistor is 1/gm. For the given values,
W gm = 2μnCox L ID
=√2×0.2×10×0.1=0.632mA/V 1 = 1.6 k
gm
(b) Replacing the BJT with its hybrid-π model results in the equivalent circuit in Fig. 2. Observing that the controlled-source gmvπ appears across its control voltage vπ , we can replace it by a resistance 1/gm, as indicated. Next the two parallel resistances 1/gm and rπ can be combined as
1 ×rπ
gm =rπ=rπ=re
1 +rπ 1+gmrπ β+1 gm
Thus, the diode-connected BJT has a small-signal resistance re. For the given data,
re = VT = 25mV =250 IE 0.1 mA
8.22 Refer to Fig. 8.11. IC1 ≃ IREF = 0.1 mA
Vx = VBE3 +VBE1 = 1.187 V If IREF is increased to 1 mA, VBE1 = 0.7
IC3 ≃ 0.02 mA
1 VBE3 = 0.7 − 0.025 ln 0.02
Vx = 1.3 V
Thus,
△Vx =1.3−1.187=0.113V
WhenVO =Vx,theEarlyeffectonQ1 andQ2 will be the same, and
IO =IREF/(1+2/β2) Thus, IO will be
IREF =100μA⇒IO = 100 = 1 + (2/1002)
99.98 μA, for an error of −0.02 μA or −0.02%. 1
IREF = 1 mA ⇒ IO = 1 + (2/1002) =
0.9998 μA, for an error of −0.0002 mA or −0.02%. For proper current-source operation, the minimum required voltage at the output is the value needed to keep Q3 in the active region, whichisapproximately0.3V.
8.23
IREF
IB3
X Q3 IO1 IO2 IO3 IOn
1 mA
Q1
IC1
IO
b
IE3
nIO
b
Q
Q Q Q2n 22 23
21
VBE1 = 0.7 − 0.025 ln
0.1 mA
= 0.642 V
This figure belongs to Problem 8.21, part (b).
Figure 2
IO1 =IO2 =IO3···=IOn =IO =IC1
The emitter of Q3 supplies the base currents for
all transistor, so IE3 = (n+1)IO
β
IREF =IB3 +IO = β(β+1) +IO
ix =αie1 +(1−α)ie3
= αie + (1 − α) × 2(1 − α)ie = ie[α + 2(1 − α)2] But2(1−α)2 ≪α.Thus,
ix ≃αie
vx =ie3 re3 +ie1re1
(n+1)IO
(1) +i αVT
Chapter 8–9
≃ 1 1+n+1
β2
For the deviation from unity to be kept ≤ 0.2%
n+1 ≤0.002 β2
⇒n =0.002×1502 −1=44 max
8.24 Refer to Fig. 8.11 and observe that
IC1 ≃IREF andIC2 =IC1;thuseachofQ1 andQ2 is operating at a collector bias current approximately equal to IREF. Transistor Q3 is operating at an emitter bias current
I =I +I =2I=2I/β=2(1−α)I E3B1B2BC αC
= 2(1−α)IREF α
Replacing each of the three transistors with its T model and applying an input test voltage vx to determine Rin, we obtain the equivalent circuit shown.
IO = IREF
1
1+ (n+1)
=2(1−α)i αVT e2(1−α)I
v=αi VT +VT x eIREF IREF
eI
REF
REF
β (β + 1)
Now, using ix = αie from Eq. (1), we have vx =ix × 2VT
IREF
Thus,
Rin ≡ i = I
vx 2VT x REF
Q.E.D. For IREF = 100 μA = 0.1 mA,
Rin = 2 × 25 mV = 500 0.1mA
8.25 ForI =10μA:
I 10μA
gm = V = 25 mV = 0.4 mA/V
T
rπ = β = 100 = 250 k
gm 0.4 mA/V
ro = VA = 10 V = 1 M
C3 x B3
ai e3
r e3
E3
I 10 μA
A0 =gmro = VA = 10V =400V/V
ix
VI 0.025 V For I = 100 μA :
gm = 100μA =4mA/V 25 mV
Out C2
aie2
100 =25k 4 mA/V
C1
ie3 aie1
v
x
rπ =
ro= 10V =100k
ve
e1 ie2 0
B
re1
B
1
ib1
ib2
2
100 μA
A =4mA/V×100k=400V/V
i
re2
In this equivalent circuit,
re1 =re2 =re =VT =αVT =αVT
IREF
VCC
Q1
I
IE IC re3 = VT = αVT
v
o
IE3 2(1 − α)IREF ie1 =ie2 =ie
ie3 = ib1 +ib2 = 2(1−α)ie From the figure we obtain
vi
For I = 1 mA: vo 1mA vsig
= rπ × −gm(ro ∥ RL) rπ +Rsig
gm = 25mV =40mA/V rπ = 100 =2.5k
25
=−25+5 ×4(1000k∥100k)
= −303 V/V
8.27 2VA 2VA′L 2×10×0.5
A0=V =V = 0.2 =50V/V
OV OV
gm = 2ID VOV
2 = 2ID ⇒ ID = 0.2 mA 0.2
I =1k′WV2 D 2nLOV
0.2 = 1 × 0.4 × W × 0.22 2L
⇒ W = 25 L
W=12.5μm
8.28 From Eq. (8.46) we see that A0 is inversely
Chapter 8–10
40 mA/V
ro = 10V =10k
1 mA
A0 =40mA/V×10k=400V/V
8.26 Refer to Fig. 8.13(b).
gm = IC = I = 0.5 mA = 20 mA/V
VT VT 0.025 V
ro = VA = 100V =200k
I 0.5 mA C
β 100
Rin =rπ = g = 20mA/V =5k
m
Avo = −A0 = −gmro = −20×200 = −4000 V/V
Ro =ro =200k
To raise Rin by a factor of 5 by changing I , the value of I must be lowered by the same factor to I = 0.1 mA.
Now, gm is reduced by a factor of 5 and ro is increased by a factor of 5, keeping Av o unchanged at −4000 V/V. However, Ro will be increased to
Ro =5×200k=1M
If the amplifier is fed with a signal source having Rsig = 5 k and a 100-k load resistance is connected to the output, the equivalent circuit shown below results.
proportional to ID =100μA ID =25μA
ID =400μA
ID . Thus
A0 =50V/V
A0 =100V/V A0 =25V/V
I
gm
rπ
ro
A0
10 μA
0.4 mA/V
250 k
1 M
400 V/V
100 μA
4.0 mA/V
25 k
100 k
400 V/V
1 mA
40 mA/V
2.5 k
10 k
400 V/V
ID. Thus changing ID from 100 μA to 25 μA reduces gm by a factor of 2. Changing ID from 100 μA to 400 μA
From Eq. (8.42), gm is proportional to increases gm by a factor of 2.
2VA 8.29 A0 = V
2VA′ L = V
OV
OV 2×5×L
20 =
0.2
⇒ L = 0.4 μm
2ID 2I gm=V =V
OV OV
This figure belongs to Problem 8.26. Rsig 5 k
vsig
rp vp 25 k
vo 100 k
gmvp gm 4 mA/V
ro
1 M
RL
2= 2I 0.2
⇒ W = 4.21 L
V2 D 2 n ox L OV
I = μC
0.2 = 1 × 0.4 × W × 0.04
8.33gm= D= VOV
2×0.1
=1mA/V
0.2
Chapter 8–11
⇒ I = 0.2 mA
1 W
⇒W =4.21μm 2I
2L ⇒ W = 25
L
8.30
From Table K.1 (Appendix K), for the 0.18-μm
process we have |VA′|=5V/μm,μnCox =387μA/V2
Thus, for our NMOS transistor whose L=0.3μm,
VA =5×0.3=1.5V
ro = VA = 1.5 V = 15 k
ID 0.1 mA
A0 =gmro =1×15=15V/V
I=1μCWV2 D 2noxLOV
100 = 1 × 387 × W × 0.22 2L
⇒ W = 13 ⇒ W = 3.9 μm L
8.34 For the BJT cell: gm=IC= IC
VT 0.025 V
VA 100 V ro=I = I
CC
VA 100 V
A0 =gmro = V = 0.025V =4000V/V
T
Rin = rπ = β = 100 gm gm
For the MOSFET cell:
The highest instantaneous voltage allowed at the drain is that which results in a voltage equal to (VOV ) across the transistor. Thus
vOmax =1.8−0.2=+1.6V 8.31 For the npn transistor,
I gm= C =
0.1 mA 0.025 V
=4mA/V For the NMOS transistor,
gm = 2 ID VOV
4 = 2 ID 0.25
⇒ID =0.5mA
8.32 gm = 2ID = 2×0.1 =0.4mA/V
VOV 0.5
From Table J.1 (Appendix J), we find that for the 0.5-μm process |VA′ | = 20 V/μm. Thus for our 1-μ-m long transistor, VA = 20 V.
ro=VA = 20V =200k ID 0.1 mA
A0 =gmro =0.4×200=80V/V From Table J.1:
μnCox = 190 μA/V2
Now,
VT
W
gm = 2μnCox L ID = 2×0.2×40×ID
= 16ID =4 ID mA/V (ID inmA)
VA 10 V ro = I = I
DD
40
A0 =gmro = √I V/V (ID inmA)
Rin = ∞
D
BJT Cell
MOSFET Cell
Bias current
IC =0.1 mA
IC =1 mA
ID = 0.1 mA
ID = 1 mA
gm (mA/V)
4
40
1.26
4
ro (k)
1000
100
100
10
A0 (V/V)
4000
4000
126
40
Rin (k)
25
2.5
∞
∞
1 W I=μC V2
D 2 n ox L OV
100 = 1 × 190 × W × 0.25 2L
8.35 Using Eq. (8.46),
VA′ 2(μnCox) (WL)
(c) If the device is redesigned with a new value of W so that it operates at
VOV =0.25V for ID =100μA,
Chapter 8–12
A0= ID
5√2 ×0.4×8×0.54×0.54
gm = 2ID VOV
A0 =gmro =0.8×18=14.4V/V
(d) If the redesigned device in (c) is operated at
= 2×0.4×8I =2.53 I 0.08V,gm decreasesbyafactorof DD√
18 =
⇒ID=0.144mA
8.36 gm = 2μnCox
= 0.2 mA = 0.8 mA/V 0.25 V
ID
VA′ L D
5 × 0.36
ro= I = 0.1 =18k
W ID
L√
10 μA, VOV decreases by a factor equal to 10 to
ID =25μA,
ID =250μA,
ID =2.5mA,
√
gm =2.53 0.025=0.4mA/V
√
gm =2.53 0.25=1.26mA/V
√
gm =2.53 2.5=4mA/V
10 to 0.253 mA/V, ro increases by a factor of 10 to 180 k, and A0 becomes
0.253 × 180 = 45.5 V/V
√
ro = VA = VA′L = 5×0.36 = 1.8
which is an increase by a factor of 10.
(e) ThelowestvalueofA0 isobtainedwiththe
first design when operated at ID = 100 μA. The resulting A0 = 4.55 V/V. The highest value of A0 is obtained with the second design when operated atID =10μA.TheresultingA0 =45.5V/V.Ifin any design W/L is held constant while L is increased by a factor of 10, gm remains unchanged but ro increases by a factor of 10, resulting in A0 increasing by a factor of 10.
ID ID ID A0 = gmro
ID
1.8
ID =25μA ro = 0.025 =72k
A0 = 0.4 × 72 = 28.8 V/V 1.8
ID = 250 μA ro = 0.25 = 7.2 k A0 = 1.26 × 7.2 = 9.1 V/V
ID =2.5mA ro = 1.8 =0.72k 2.5
A0 =4×0.72=2.88V/V 8.37
L=0.36μm, VOV =0.25V, ID =10μA (a) gm = 2ID = 2×10 =80μA/V
8.38 2V 2V′L A= A= A =
2×6×0.5 0.15
100= 1 ×400× W ×0.152 2 L
⇒ W = 22.2 L
Thus,
W =22.2×0.5=11.1μm
=40V/V
0 VOV VOV 1W
I = k′ V2 D 2n L OV
VOV
r = VA = VA′ L o ID ID
0.25
FromAppendixJ,TableJ.1,VA′ =5V/μm, ro = 5×0.36 = 0.18 M
10
A0 = gmro = 80×0.18 = 14.4 V/V
gm = 2ID = 2×0.1 =1.33mA/V VOV 0.15
r = VA′L = 6×0.5 =30k
(b) IfI isincreasedto100μA(i.e.,byafactor D√o
of 10), VOV increases by a factor of 10 = 3.16 to
VOV =0.25×3.16=0.79V
and gm increases by a factor of 10 = 3.16 to gm =80×3.16=253μA/V=0.253mA/V and ro decreases by a factor of 10 to
ro = 0.18 M = 18 k 10
Thus, A0 becomes
A0 =0.253×18=4.55V/V
ID 0.1 8.39 A0 =|Avo|=100
100=2VA =2VA VOV 0.2
⇒VA =10V
Since VA′ = 20 V/ μm, we have
VA 10
L=VA′ =20=0.5μm
I =1k′WV2 D 2 n L OV
√
Chapter 8–13 1WW
50 = 2 × 200 × L × 0.22 ⇒ L
W 1W
⇒ L =12.5
8.40 Refer to Fig. 8.15(a).
V =|V |+|V |=0.5+0.3=0.8V SG2 tp OV
|VOV|2
= 8 ID2 = 2μpCox L
× 0.252 L 2
8.42 Refer to Fig. P8.42. The gain of the first stageis
Av1 =−gm1(ro1/2)
where (ro1/2) is the equivalent resistance at the
output of Q1 and includes ro1 in parallel with the output resistance of the current-source load, which is equal to ro1. Similarly, the gain of the second stage is
Av2 =−gm2(ro2/2)
Now because VAn = |VAp| = |VA| and both Q1 and
Q2 are operating at equal currents I , we have ro1 =ro2 =ro
TheoverallvoltagegainAv willbe
Av = Av1Av2
Av = 1 gm1gm2ro2 ID0.1 4
100 =
2
× 100 ×
1
2
1 W
VG =2.5−VSG2 =2.5−0.8=1.7V 2
W
L =32
I=1μCWV2 D1 2 n ox L OV1
100= 1 ×200× 2
1 W
L 1
×0.32
⇒
I D2
W L 1
= 11.1
= 1 μ C 2 p ox
W L
2
|V OV2
|2 ×0.32
W 2L2
W ⇒ L
100= 1 ×100×
= 22.2
Av =−gm1 (ro1∥ro2)
2
2ID 2×0.1 gm1 = V = 0.3
= 0.67 mA/V
ro1 = ro2 = |VA′|L = 20×0.5 = 100 k
OV
Av =−0.67×(100∥100)=−33.5V/V
If the two transistors are operated at equal overdrive voltages, |VOV |, both will have equal gm,
8.41 Refer to Fig. 8.15. Since V′ = |V′ | and Av = 1(gmro)2 AnAp 4
the channel lengths are equal, VAn = |VAp| and ro1 =ro2 =ro.Thus
and
2×5 10 gmro = |VOV | = |VOV | = |VOV |
Av = −gm1(ro1 ∥ ro2) = −gm1(ro/2) 1
2|VA|
1 10 2
−40=−2gm1ro ⇒gm1ro =80
Av =400=4× |VOV| ⇒ |VOV | = 0.25 V
2V 2V′L A0 = An = An VOV VOV
80= 2×5×L 0.25
⇒ L = 2 μm
VSG2 =|Vtp|+|VOV|=0.5+0.25=0.75V VG =VDD −VSG2 =1.8−0.75=1.05V
×0.252
8.43
3 M
200 A ID
IR
2 M V
GS
1 W
I = μ C V 2
D1 2 n ox L OV 1
1 W 100= ×400×
2L1
Figure 1
(a) Neglecting the dc current in the feedback network and the Early effect, we see from Fig. 1 that ID = 200 μA. Now, using
R 1 + G2
RG1 3
=0.95× 1+2 =2.375V
The MOSFET will remain in saturation as long as
VDG ≥ −Vt . Thus at the limit VDG = −0.5 V, vGmax = 0.5 + vDmin
Chapter 8–14
VDS = VGS
1 W I=μC V2
D 2 n ox L OV
we can determine VOV :
0.2 = 1 × 2 × V 2 2 OV
⇒VOV =0.45V
VGS = Vt +VOV = 0.5+0.45 = 0.95 V
The current in the feedback network can now be found as
VGS +|vˆi|=0.5+VDS −|vˆo| 0.95 + |vˆo| = 0.5 + 2.375 − |vˆo|
VGS 0.95 IR = 2M = 2
=0.475μA
o 1 1 + |Av |
Substituting |Av | = 86.5, we obtain |vˆo| = 1.9 V
An approximate value of |vˆo| could have been obtained from
vOmin = VOV = 0.45 V
Thus,
VDS −|vˆo|=VOV
⇒|vˆo|=VDS −VOV =2.375−0.45 = 1.925 V
|vˆo|
|vˆi| = 86.5 = 22 mV
(c) To determine Rin, refer to Fig. 2,
vi vo − vi ii=R − R
G1 G2 =vi −Avvi−vi
|Av |
|vˆ | = 0.5 + 2.375 − 0.95
which indeed is much smaller than the 200 μA delivered by the current source. Thus, we were justified in neglecting IR above.
(b) Replacing the MOSFET with its hybrid-π model, we obtain the equivalent circuit shown in Fig. 2.
i
i
RG23M vovi
viR vRG2 G1 gs
rv gmvgs oo
2 M
Rin vgs vi
Figure 2
A node equation at the output node yields
vo + g v + vo − vi = 0 r mgs R
RG1
1
RG2
(1−A )
= vi +
RG1 RG2
v
oG2
wherevgs=vi.Thus, 111
Rin=vi =1 1 +(1−Av) ii RG1RG2
1 (1+86.5)
+ = 33.7 k
=−vi gm −
v1 23
vo + ro
RG2
o =− gm− (ro∥RG2)
RG2
= 1
vi RG2
gm = 2ID = 2×0.2 =0.894mA/V
8.44 Refer to Fig. 8.16(a). Ro =100k=ro1∥ro2 But
|VA| 5 ro1 = ro2 = I = I
REF REF
Thus,
100= 1 × 5
2 IREF ⇒IREF =25μA
Av =−gm1Ro
VOV 0.45 VA 20
ro = I = 0.2 = 100 k
D 1
vo
v =− 0.89− 3000 ×(100∥3000)
i
=−86.5V/V
To obtain the maximum allowable negative signal swing at the output, we first determine the dc voltageattheoutputbyreferringtoFig.1,
−40 = −gm1 × 100 ⇒ gm1 = 0.4 mA/V
But gm1 =
Thus,
k′n 1 1
k′p |VOV3|2 VDD 1 + |VAp|
vO 1−V +|V |
(vI −Vtn)2
Chapter 8–15
W
2μnCox L
W
ID1
1
L1
1 W I=μCV2
=DDAp 1+ VO
0.4= 2×0.4 W
⇒=8 L1
×0.025
VAn
200 65×0.5262
1 (v −0.6)2 =
1− vO 5+10
vO 1 + 20
5 I 10
1 +
7.41(v − 0.6)2 = 1 − 0.07vO
D1 2 n ox L OV1
1 1+0.05vO
25 = 1 × 400 × 8 × V 2
2 OV1
⇒VOV1 =0.125V
If Q2 and Q3 are operated at |VOV | = 0.125 V,
I
Substituting vO = VOA = 4.47 V gives
1 W ID2 = ID3 = μpCox
vI =VIA =0.88V
To find the coordinates of point B, we note that
VOB = VIB − 0.6. Thus 7.41V2 = 1−0.07VOB
OB 1 + 0.05 VOB
This equation can be solved by trial and error to
yield VOB=0.36V and
VIB = 0.96 V
Thus at the output the linear region now extends from 0.36 V to 4.47 V as compared to 0.335 V to 2.47 V when the power supply was 3 V: an increase of about the same size as the increase in the power supply.
8.47 Refer to Fig. 8.16(a).
Note that Q2, Q3 are not matched: ID1 = 100 μA
(a) ID2 =ID1 =100μA
ID3 = (W/L)3 = W3 ID2 (W/L)2 W2
(Note that VSG2 = VSG3)
⇒ID3 =100μA 10 =25μA⇒ IREF =25μA
40
(b) By referring to Fig. 8.16(d), you notice that in Segment III, both Q1 and Q2 are in saturation and the transfer characteristic is quite linear. The output voltage in this segment is limited between VOA and VOB: coordinates of point A:
vOA =VDD −|VOV3|
25= ×100× 2
L 2,3
2 L2,3
|VOV |2 ×0.1252
1 W
⇒
W L 2,3
= 32
8.45 From the results of Example 8.4, we see that the almost linear region of the transfer characteristic (i.e., region 3) is defined by
VIA = 0.89 V and VIB = 0.935 V. Maximum output signal swing is achieved by biasing Q1 at the middle of this range; thus
VI =0.913V
The peak-to-peak amplitude at the output will be
(VOA − VOB) = 2.47 − 0.335 = 2.135 V. Thus the peak amplitude will be 1 (2.135) = 1.07 V.
2
8.46 Refer to the solution to Example 8.4.
VOA =VDD −|VOV3|
= 5−0.526 = 4.474 ≃ 4.47 V
The relationship between vO and vI in region III
of the transfer characteristic can be found as
follows: 1Wv
k′n (vI−Vtn)2 1+O 2 L1 VAn
1W V−v = k′ (V −|V|)2 1+ DD O
2pLSGtp |V| 2 Ap
2 ID3 25 |VOV3|=1 W=1
Forv =1.65V,from⃝1wehave O
(vI −0.8)2 =0.11(1−0.03×1.65)⇒vI =1.123V
∂vO = −195.8 V/V ∂vI vI=1.123
(e) Rout = ro1 ∥ ro2
ro1 = VAn = 100 V = 1 M
ID1 0.1 mA
ro2 = VAp = 50V =500k
ID20.1mA ⇒Rout =500k∥1M
Rout=333k
2k′p L 3 |=0.32V
10 2×50× 1
Chapter 8–16
⇒ |V
OV 3
VOA = 3.3 − 0.32 = 2.98V
At point B: VOB = VIB − Vtn
Now we find the transfer equation for the linear
section: (Refer to Example 8.4)
iD1 =iD2 ⇒ (Notethat|VOV2|=|VOV3|)
1W v k′ (v−V)2 1+ O
2 n L I tn V
1 An
1W V−v =k′ V21+DDO
2 p L OV3 |V |
2AP ′W
1 20 v gm1 = 2kn L ID1
×100× (vI −0.8)2 1+ O
2 1 100
1
1 40 3.3−v = ×50× ×0.322 1+ O
2 1 50
2 2vOvO
= 2×100×10−6×20×100×10−6 1
= 0.632 mA/V
Av =−gm1(ro1 ∥ro2)=−210.6V/V
Comment: The three estimates of voltage gain obtained in (c), (d) and (e) are all reasonably close; about −200 V/V.
(vI −0.8) =0.32 1.066−50
1 − 0.019v (vI − 0.8)2 = 0.11 O
(vI – 0.8)2 = 0.11(1 − 0.03vO)
1+100
(1) 8.48 (a)
≃ 0.11(1 − 0.03vO )
1 + 0.01vO
NowifwesolveforVOB =VIB –0.8
V2 +0.0033V −0.11=0⇒V =0.33V OB OB OB
Therefore the extreme values of vO for which Q1
andQ2 areinsaturation0.33V≤vO ≤2.98V VG
(c) From (b) we can find VIA and VIB:
VIB =VOB +Vt =0.33+0.8=1.13V
If we solve (1) for VOA = 2.98 V, then
(VIA − 0.8)2 = 0.11(1 − 0.03 × 2.98) ⇒ VIA
= 1.116 V
Large-signal voltage gain
= vO = 2.98 − 0.33 vI 1.13 − 1.116
vO
v
(d) vO = 2 = 2 =1.65V Differentiating both sides of (1) relative to vI :
2(vI −0.8)=0.11×(−0.03)∂vO ∂vI
⇒∂vO =−606.1(vI−0.8) ∂vI
1.0 V
Q2 ID2
VD
R
0
i
= −189.3 V/V VDD 3.3
ID1 Q1
1.0 V Figure 1
From Fig. 1 we see that since the dc currents into the gates are zero,
VD = VG
Also, since Q1 and Q2 are matched and carry
equal drain currents, ID1 =ID2 =ID
VSG2 =VGS1 =1V and thus,
VG =0
Thus,
1
ID = 2 ×1×(1−0.5)2 = 0.125 mA
(b)
R=vi=vi =R1
Chapter 8–17
vgs GD
in
ii R
(vi − vo)/R 1 − vo vi
gmvgs
R
=
1000 = 13.3 k 1 + 74.1
vo
=
(d) v =R +R =20+13.3=0.4V/V
vi
2gmvgs
gmvgs
1 − Av vi
vgs
Rin 13.3 sig in sig
Gv=vo =vi ×vo vsig vsig vi
= 0.4 × −74.1 = −29.6 V/V
(e) Both Q1 and Q2 remain in saturation for output voltages that ensure that the minimum voltage across each transistor is equal to
|VOV | = 0.5 V. Thus, the output voltage can range from −0.5 V to +0.5 V.
From Fig. 2 we see that vo =vi −2gmvgsR
But
v =v
3 − VBE3 8.49 (a) IREF =IC3 = 46k
IREF = 3−0.7 46
= 0.05 mA
⇒IC2 =5IC3
IC2 =I=0.25mA⇒I=0.25mA
vgs vi Figure 2
gs i
Thus,
Av =vo =1−2gmR vi
gm = 2ID = 2×0.125 =0.5mA/V VOV 1−0.5
Av =1−2×0.5×1000=−999V/V (c)
ii R
3V
46 k
3V
Q1
Q2
vi vgs 2gmvgs ro/2vo
R vi in ii
vgs vi
Figure 3
ForthecircuitinFig.3wecanwriteattheoutput
vo +2gmvgs+vo−vi =0 ro/2 R
Substituting vgs = vi and rearranging, we obtain
IREF
vi
vo
Q3
I
I 0.25
(b) |VA|=50V⇒ro1 = |VA| = 30
=120k
ro2 = 30 =120k
vo = −2g vm12
1 − 1 2gmR
0.25
Total resistance at the collector of Q1 is
equal to ro1 ∥ ro2, thus
rtot =120k∥120k=60k
(c) gm1 = IC1 = 0.25 =10mA/V VT 0.025
r =β=50=5k π1 gm 10
i +
R ro
But2gmR≫1;thus
vo ro Av=v≃−2gm R∥2
i
|VA| ro = I
where
(d) Rin =rπ1 =5k
Ro =ro1 ∥ro2 =120k∥120k=60k Av =−gm1Ro =−10×60=−600V/V
20
= 0.125 =160k
D
Av =−2×0.5(1000∥80)=−74.1V/V
8.50
L = 2×0.367 = 0.734
Again, to use a multiple of 0.18 μm we select
L = 0.9 μm. This represents an increase in L by a
factor of 0.90 = 5 . Ws will have to increase by 0.54 3
Chapter 8–18
the same factor. Thus, the area of each transistor
and the total
Initial total area =
AreaofQ1 + AreaofQ2 + AreaofQ3
= 6.46 × 0.542 + 29.1 × 0.542 + 29.1 × 0.542 = 18.85 μm2
New total area =
6.46×0.92 +29.1×0.92 +29.1×0.92
= 52.37 μm2
Thus, the increase is by a factor of 2.78.
8.51 Refer to Fig. 8.18. Rin = ro + RL
will increase by a factor of area will increase as follows:
52 3
For an output of 1.6 V,
VSD2min = |VOV2| = 1.8 − 1.6 = 0.2 V,
For an output of 0.2 V,
VDS1min = 0.2 V,
thus
VOV1 =0.2V
SinceID2 =ID3 =ID1 =50μA 1
1+gmro
= 20+20 =980
andI = μ C (W/L)V2 ,wehave D2pox OV
W W 2ID2
L = L =μC (V )2
1+2×20
Rout =ro +Rs +gmroRs
2 3pOXOV 2 (50 μA)
= 20+1+2×20×1 = 61 k vo = RL
= 86 μA/V2 (0.2 V)2 = 29.1 For Q1,
W
vsig Rs + Rin
2 (50 μA)
= 387 μA/V2 (0.2 V)2
gm1 = 2ID = 2×0.05 =0.5mA/V VOV 1 0.2
ro1∥ro2 = 10 =20k 0.5
=
20 1+0.98
= 10.1 V/V
L
Av must be at least −10 V/V and Av = −gm (ro1 ∥ ro2)
= 6.46
1
8.52
io
R 20 k L
But
ro1=A1=An= =100L
V V′L 5L ID1 ID1 0.05
io
|V| |V′|L 6L
isig
20 k
ro2 = A2 = Ap = ID2 ID2
= 120L 0.05
Rs
Thus,
100L ∥ 120L = 20 k
⇒ L = 0.367 μm
If L is to be an integer multiple of 0.18 μm, then L = 0.54 μm
Toraisethegainto20V/V,ro1∥ro2 hastobe raised to 40 k, which requires
Rin
Rin = ro +RL = 20+20 =980
1+gmro 1+2×20 Since is = io,
io = Rs = 20 =0.95A/A isig Rs + Rin 20 + 0.98
IfRL increasesbyafactorof10,Rin becomes 20 + 200
0.1= 1 ×4×V2
2 OV 1
⇒VOV1 =0.224V
VGS1 = Vt +VOV1 = 0.8+0.224 = 1.024 V
VBIAS =VGS +ID1Rs
= 1.024+0.1×0.05 = 1.03 V
(b) g = 2ID1 = 2×0.1 =0.9mA/V m1 VOV 1 0.224
All transistors are operating at ID = 0.1 mA and have |VA| = 20 V. Thus all have equal values for ro:
Rin = 1+2×20 =5.37k and the current gain becomes
Chapter 8–19
io = 20 =0.79A/A isig 20+5.37
ThusanincreaseinRL byafactorof10resulted in a decrease in the current gain from 0.95 A/A to 0.79 A/A, a change of only −17%. This indicates that the CG amplifier functions as an effective current buffer.
8.53 Refer to Fig. P8.53.
ID =0.2mA VOV =0.2V
gm=2ID =2×0.2=2mA/V VOV 0.2
ro = VA = 20 = 100 k ID 0.2
Rout =ro +Rs +gmroRs
500 = 100+Rs(1+2×100)
400
⇒ Rs = 201 ≃ 2 k
V = I R + V BIAS D S GS
=IDRS +Vt +VOV
= 0.2×2+0.5+0.2 = 1.1 V
8.54 Refer to Fig. P8.54. To obtain maximum output resistance, we use the largest possible Rs consistent with IDRs ≤ 0.3 V. Thus
0.3V
Rs = 0.1 mA = 3 k
ro = |VA| = 20 =200k ID 0.1
(c) ForQ2,RL =ro2 =200k, Rin = ro + RL
1+gmro = 200+200
1+0.9×200
(d) Rout =ro +Rs +gmroRs
= 200+0.05+0.9×200×0.05 = 209 k
= 2.2 k
(e) vi = vsig
Rin = 2.2
Rin + Rs 2.2 + 0.05
= 0.98 V/V
vo =RL =200=90.9V vi Rin 2.2
vo = 90.9×0.98 = 89 V/V vsig
Now, for Q2 we have gm =1mA/V and Thus,
(f) The value of vo can range from
VBIAS −Vt =1.03−0.8=0.23Vto
(VDD − VOV 2). Since ID2 = ID1 and kn = kp, then VOV 2 = VOV 1 . Thus the maximum value of vo is 3.3 − 0.224 = 3.076 V. Thus the peak-to-peak valueofvo is3.076−0.23=2.85V. Correspondingly, the peak-to-peak value of vsig will be
vsig (peak to peak) = 2.85 = 32 mV 89
VA =10V ro=VA = 10V =100k
8.56 Given Eq. (8.63):
ID 0.1 mA
R =r+R+grR
R ≃r in e
ro+RL RL
out o s mos = 100 + 3 + 1 × 100 × 3 = 403 k
ro+β+1 We can write
Rin = re
1 + (RL/ro) = 1 + [RL/(β + 1)ro]
1 + (RL/ro) 1 + (RL/101ro)
RL /ro
0
1
10
100
1000
∞
Rin /re
1
2
10
50.8
91.8
101
8.55 Refer to Fig. P8.55.
(a) ID1 =ID2 =ID3 =100μA
Using I = 1k′ (W/L) V2 , we obtain D1 2 n 1 OV1
ObservethattherangeofRin isre to(β+1)re.
8.57R ≃r ro+RL
in e ro + RL/(β + 1)
Rin ≃2re isobtainedwhen
Thus,
i=−isig 1 + 1 + 1
re ro Rsig
and
1/ro
1 sig1+1+1
re ro Rsig
At the collector node, we can write
io ≡ kisig = i1 − αi
Thus,
ki =i 1/ro +(α/re) (1) sig sig1+1+1
re ro Rsig
Nowro ≫re andforthecaseRsig ≫re,weobtain
k≃ α/re =α 1/re
For our case,
α= β
β + 1
k=α= β =100=0.99 β+1 101
TheoutputresistanceRout isgivenby Rout =ro +(Rsig∥rπ)(1+gmro) where
ro=VA = 50V =500k
Chapter 8–20
1/re
ro + RL
ro +RL/(β+1)
⇒ RL ≃ ro
= 2
i = i
8.58 Equation (8.66):
Rout = ro +(Re ∥rπ)+(Re ∥rπ)gmro
= ro + (re ∥ rπ )(1 + gm ro )
For gmro ≫ 1,
R ≃r +g r (R ∥r ) out o moeπ
Rout =1+ gmrπRe ro rπ +Re
=1+ βRe (β+1)re +Re
Thus,
Rout =1+ β(Re/re)
ro β + 1 + (Re/re) Forβ=100,
Rout =1+ 100(Re/re) ro 101+(Re/re)
Observe that Rout ranges from ro to (β + 1)ro, with the maximum value obtained for Re = ∞.
8.59 Refer to Fig. P8.59. To obtain the short-circuit current gain k, we replace the BJT with its T model and short circuit the collector to ground, resulting in the circuit shown in the figure.
IC IC
0.1 mA 0.1 mA
Re /re
0
1
2
10
β/2
β
1000
Rout /ro
1
2
2.9
10
34
51
92
gm = V T
E
Rsig
io kisig
ro
i1
= 0.025 V = 4 mA/V gmro =4×500=2000
β 100
rπ = g = 4 = 25 k
m
Thus,
Rout = 500+(10∥25)×2001 = 14.8 M
Thus the CB amplifier has a current gain of nearly unity and a very high output resistance: a near-ideal current buffer!
A more exact value of k can be obtained using Eq. (1); k = 0.975.
8.60 Refer to Fig. P8.60.
I=IC =αIE =0.99×5−0.7≃1mA
4.3 ro = VA = 100V =100k
IC 1 mA
Rout = ro + (RE ∥ rπ )(1 + gmro)
ai i
re
isig
At the emitter node we see that there are three parallel resistances to ground: re, ro, and Rsig.
where
gm = IC = 1mA =40mA/V VT 0.025 V
gmro = 40×100 = 4000
β 100
rπ=g =40=2.5k
m
RE = 4.3 k
Thus,
Rout = 100+(4.3∥2.5)×4001 = 6.4 M
For
8.63 Refer to Fig. 8.32 Ro = gm3ro3ro4
For identical transistors,
Q.E.D.
Chapter 8–21
Ro = (gmro)ro 2|VA | |VA |
=|VOV|× I Thus,
2|VA |2 IRo = V
OV
(a) I = 0.1 mA
△VC =10V 10V
2×42 0.1×Ro = 0.2 =160
Ro = 1.6 M
To obtain the W/L values,
1 W I =ID = 2μpCox L
△I = 6.4M =1.6μA
A very small change indeed!
8.61 Refer to Fig. 8.27.
Rout =ro +(Re ∥rπ)(1+gmro) ≃ ro + (Re ∥ rπ )(gm ro )
Rout
r =1+gm(Re∥rπ)
o
=1+ gmrπRe
3,4 1 W
|VOV|2 ×0.22
100= ×100×
2 L3,4
rπ +Re =1+ βRe
W
⇒ = 50
L 3,4
(b) I = 0.5 mA
2×42
0.5Ro = 0.2 = 160
Ro = 320 k
1 W
(β/gm) + Re For our case β = 100,
IC 0.5 mA
gm = V = 0.025V =20mA/V,thus
T 1W
|VOV |2
I = 2μpCox L |VOV|2 3,4
Rout =1+100Re ro 5+Re
where Re is in kilohms.
(a) For Rout = 5 ro, Eq. (1) gives
Re =0.208k=208
(b) For Rout = 10 ro, Eq. (1) gives
Re =0.495k≃500.
(1)
500 = 2 × 100 × L
3,4
W L 3,4
8.64 Refer to Fig. 8.32.
Ro = (gm3ro3)ro4
For identical transistors,
Ro = (gmro)ro
= 2|VA| × |VA| |VOV | I
Thus,
2|VA |2 IRo=|VOV|
Substituting
| V A | = | V A′ | L
2|V′|2 IRo = A L2
⇒
= 250
(c) ForRout =50ro,Eq.(1)givesRe =4.8k. From Eq. (1) we see that the maximum value of Rout/ro is obtained with Re = ∞ and its value is 101, which is (β + 1).
8.62 50 = gm2ro2 = A02 = 2VA
VOV
VA =50×VOV/2
= 25 × 0.2 = 5 V
V A = V A′ L
5 = 5 × L ⇒ L = 1 μm
|VOV |
Q.E.D.
Now, for L=0.18μm,
To obtain W/L, we use
2 × 52 o 0.2
1 W ID=I= μnCox V2
×0.182 =8.1V L=0.36μm, IRo = 0.2 ×0.362 =32.4V
IR =
2 LOV 1 W
Chapter 8–22
2 × 52 2×52
250=2×400× L ×0.252 ⇒ W = 20
L = 0.54μm, IRo = 0.2 ×0.542 = 72.9 V
L
To obtain maximum negative signal swing at the output, we select VG so that the voltage at the drain of Q1 is the minimum permitted, which is equaltoVOV (i.e.,0.25V).Thus
VG =0.25+VGS2
=0.25+VOV2 +Vt
= 0.25+0.25+0.5 = 1.0 V
The minimum permitted output voltage is VG −Vt =1−0.5=0.5Vor2VOV.
8.66 Refer to Fig. 8.33.
gm1=2ID1 = 2I =2×0.2=2mA/V
VOV1 VOV 0.2
Since all transistors are operating at the same ID and |VOV |, all have equal values of gm. Also because all have equal |VA| = 4 V, all ro’s will be equal:
ro =|VA|=|VA|= 4 =20k ID I 0.2
Ron =(gmro)ro =(2×20)×20=800k Rop =(gmro)ro =(2×20)×20=800k Ro =Ron∥Rop =400k
Av =−gm1Ro =−2×400=−800V/V
8.67 Refer to Fig. 8.33.
Av = −gm1Ro
−280=−1×Ro ⇒Ro =280k
To fill out the table we use
gm=2ID=2I=2I=10I |VOV | |VOV | 0.2
Av = gm(Ro/2)
(a) The price paid is the increase in circuit area.
(b) As I is increased, gm increases and hence the current-driving capability of the amplifier, and as we will see later, its bandwidth.
(c) The circuit with the largest area (58n) as compared to the circuit with the smallest area (0.065n): Av is 364.5/40.5 = 9 times larger; gm is 100 times larger, but Ro is 11.1 times lower.
8.65 Refer to Fig. 8.33(a). gm1 = 2ID = 2I
VOV VOV 2I
2 = 0.25
⇒I =0.25mA
For identical transistors,
2VA VA 2VA2
Ro =(gmro)ro = VOV 200 = 2VA2
0.25 × 0.25 ⇒VA =2.5V
VA′ 5
This table belongs to Problem 8.64.
I = VOV I
V A = V A′ L
L= VA = 2.5 =0.5μm
L=Lmin =0.18μm IRo = 8.1 V
L = 2Lmin = 0.36 μm IRo = 32.4 V
L = 3Lmin = 0.54 μm IRo = 72.9 V
gm
(mA/V)
Ro
(k)
Av (V/V)
2WL (μm2 )
gm
(mA/V)
Ro
(k)
Av (V/V)
2WL (μm2 )
gm
(mA/V)
Ro
(k)
Avo (V/V)
2WL (μm2 )
I = 0.01 mA W/L = n
0.1
810
−40.5
0.065 n
0.1
3,240
−162
0.26n
0.1
7,290
−364.5
0.58n
I = 0.1 mA W/L = 10 n
1.0
81
−40.5
0.65n
1.0
324
−162
2.6n
1.0
729
−364.5
5.8n
I = 1.0 mA W/L = 100 n
10.0
8.1
−40.5
6.5n
10.0
32.4
−162
26n
10.0
72.9
−364.5
58n
gm1=2ID = 2I ⇒I=1gm1VOV VOV VOV 2
= 1 ×1×0.25 = 0.125 mA 2
All four transistors are operated at the same value of ID and the same value of |VOV |. Also all have the same channel length and |VA′ |; thus all ro values are equal. Thus
Ron =Rop =2Ro =2×280=560k
560 = (gmro)ro
= 2|VA| |VA| |VOV| I
= 2|VA |2 0.25 × 0.125
⇒VA =2.96V
L= VA = 2.96 =0.6μm
× 0.252
Thus,
VG4 =VDD −VSG4 =3.3−1=2.3V
To obtain the largest possible signal swing at the output, we maximize the allowable positive signal swing by setting VD4 at its highest possible value ofVDD −|VOV|=3.3−0.2=3.1V.Thiswillbe obtained by selecting VGS as follows:
VG3 = VD4 − VSG3 Since
VSG3 =VSG4 =1V
VG3 =3.1−1=2.1V
the highest allowable voltage at the output will be vD3max=VG3+|Vtp|
= 2.1+0.8 = 2.9 V
Since both Q3 and Q4 carry the same current
I = 100 μA and are operated at the same overdrive voltage, |VOV | = 0.2 V, their W/L ratios will be the same and can be found from
Chapter 8–23
VA′ 5
For each of the NMOS devices,
1 W I=μC V2
D 2 n ox L OV 1,2
1 W ID = μpCox
1 W
|VOV|2 3,4
W
L × 0.22
3,4
125 = 2 × 400 × W
⇒ L =10 1,2
L
1,2
2 L 1
⇒ L = 83.3 3,4
For each of the PMOS transistors,
100 = 2 × 60 × W
1 W ID = 2μpCox L
|VOV |2
To obtain Ro, we first find gm and ro of both devices,
3,4
1 W
= 2×0.1 =1mA/V 0.2
125 = 2 × 100 × W
⇒ L =40 3,4
8.68
L
× 0.252
gm3,4 = 2ID |VOV |
Ro = (gm3ro3)ro4
= 1×50×50 = 2.5 M
3,4
|VA| D
5
ro3,4 = I = 0.1 =50k
VDD 3.3 V Q4
VD4
Q3
I 100 A
8.69
ix
VG4
VG3
Ro
Q vx
ix
2 vy
Ro
ro1 Q1
VSG4 = |Vtp| + |VOV | = 0.8 + 0.2 = 1 V
While vx appears across Ro, vy appears across ro1, Thus,
vy = ro1 vx Ro
r = o1
ro1 + ro2 + gm2ro2ro1
For gm2ro2 ≫ 1 and gm2ro1 ≫ 1,
vy ≃ 1 vx gm2 ro2
8.70 Refer to Fig. P8.70.
(a) For the circuit in (a),
(b) For the cascode circuit in (c) to have the same minimum voltage requirement at the drain as that for circuit (b), which is equal to VOVb = 2 VOV a, we must operate each of the two transistors in the cascodeamplifieratVOV =VOVa.Thuseachof the two transistors in the cascode circuit will have gm = gma. Also, each will have ro = roa. Thus
Avc = −gmRo
≃ −gm[(gmro)ro] = − A 2v a
Obviously, the cascode delivers a much greater gain than that achieved by quadrupling the channel length of the CS amplifier.
Chapter 8–24
1 W
I= μC V2 (1)
2 n ox L OVa For the circuit in (b),
8.71
1 W
I= μC V2 (2)
VDD 1.3 V Q4
2 n ox 4L OVb
Comparing Eqs. (1) and (2) we see that VOVb = 2VOVa Q.E.D.
Now,
gm = 2ID VOV
Thus for the circuit in (a), gma = 2I
VOV a
and for the circuit in (b),
gmb = 2I = 2I = I
0.7 V
0.4 V
0.9 V
VI vi 0.6 V
Q3
Q2
Q1
vo
VOVb
gmb = 1 gma 2
2 VOVa VOVa
Q.E.D.
Thus,
Since the channel length in (b) is four times that in (a),
VAb = 4VAa and
rob = 4roa Thus
Ava = −gmaroa and
Avb = −gmbrob =−1gma ×4roa
2
= 2Ava Q.E.D.
Since all four transistors have equal transconductance parameters, k, and all four have the same bias current, their overdrive voltages will be equal. We can obtain |VOV | by considering either Q1 or Q4. For Q1,
VGS =VI =0.6V=Vt +VOV Thus,
VOV = 0.6−0.4 = 0.2 V Similarly, for Q4,
VSG = VDD − VG4 = 1.3 − 0.7 = 0.6 V
Thus,
|VOV|=VSG −|Vt|=0.6−0.4=0.2V
The maximum allowable voltage at the output is
vOmax = VGS + |Vt3|
= 0.4+0.4 = 0.8 V
The minimum allowable voltage at the output is
vOmin =VG2 −|Vt2|
= 0.9−0.4 = 0.5 V
Thus the output voltage can range from 0.5 V to 0.8 V.
8.72
VG2
vi
Chapter 8–25
Rin2= ro2+RL 1 + gm2ro2
9+143.6
= 1+1.55×9 = 10.2 k
Rd1 = ro1 ∥Rin2 = 9∥10.2 = 4.8 k
A1 = −gm1Rd1 = −1.55 × 4.8 = −7.41 V/V
8.73 Refer to Fig. P8.73.
(a) R1 =ro1 =ro
R2 ≃ (gmro)ro
R 3 = R 2 + r o = g m r o2 + r o ≃ r o gm ro gm ro
(b) i1 = gmvi
v R3 ro 1
o i2=i1R+r =gmvir+r =2gmvi
I 0.2
3o oo mARo 1
Q
Q1 5.4/0.36
i3 =i1 −i2 = 2gmvi i4 = i3 = 1gmvi
2
i5 = i4 = 1gmvi 2
i6 = 0 (because vsg4 = 0) i7 = i5 = 1gmvi
2
2 5.4/0.36
Rin2 ro1
RL
(c) v1 = −i2ro = −1(gmro)vi 2
g =g = 2μC W I m1m2 noxLD
v = −i R = − 1 g (g r )r v 2 42 2mmooi
= −1(gmro)2vi 2
v3 = −i5R1 = −1gmviro = −1(gmro)vi 22
(d) vi is a 5-mV peak sine wave.
vˆ1 =−1×20×vi =−10×5=−50mV
2
Thus, v1 is a 50-mV peak sine wave that is 180◦
out of phase with vi .
vˆ2 = − 1 × 202 × 5 = −1 V
2
Thus,v2 isa1-Vpeaksinewave,180◦ outof
phase relative to vi .
vˆ3 =−1×20×5=−50mV
= 2×0.4× VA
5.4 0.36
×0.2 = 1.55 mA/V VA′ L 5 × 0.36
ro1=ro2=I = I = 0.2 =9k DD
Ro = ro1 +ro2 +gm2ro2ro1 = 9+9+1.55×9×9 = 143.6 k
Av =−gm1(Ro∥RL)
−100 = −1.55(Ro ∥ RL )
⇒Ro∥RL =64.5k
1 Ro RL 64.5
1 1
+=
1111
=−= 2
RL 64.5 143.6 117 Thus, v3 is a 50-mV peak sine wave, 180◦ out of ⇒RL =117k phase relative to vi .
vi 5 mV
0
v1 50 mV
0
v2 1 V
0
v3 50 mV
0
VDD 1.8 V
t
t
t
t
We design for a minimum voltage of |VOV | across each of Q1 and Q2.
VG1 =VDD −VSG1 =VDD −|Vtp|−|VOV| = 1.8−0.4−0.2 = 1.2 V
VG2 = VS2 − VSG2
= 1.6−0.4−0.2 = 1.0 V VG3 = VS3 − VSG3
= 1.4−0.4−0.2 = 0.8 V
All transistors carry the same ID = 0.2 mA and operate at the same value of |VOV | = 0.2 V. Thus, their W/L ratios will be equal,
0.2 = 1 × 0.1 × W × 0.22 2L
⇒ W = 100 L
Ro = (gmro)2ro where
gm= 2ID =2×0.2=2mA/V |VOV | 0.2
ro = |VA′|L = 6×0.4 =12k ID 0.2
Ro =(2×12)2 ×12=6.91M
8.75 Refer to Fig. P8.75. (a) Ro1 = ro
Ro2 = ro
Ro5 = ro
Ro4 = (gmro)ro
Ro3 = ro3 + (gm3ro3)(Ro1 ∥ Ro2)
= ro + gm ro × 1 ro 2
≃ ro (1 + 1 gm ro ) ≃ 1 (gm ro )ro 22
Chapter 8–26
8.74
VG1 Q1
ro1
1.6 V
(gm2ro2) ro1 1.4 V
R = ro3 +Ro4 in3 1 + gm3ro3
= 1 +ro ≃ro gm
≃ ro +gmroro gmro
VG2
VG3
Q2
Q3
I 0.2 mA
(b) Ro = Ro3 ∥Ro4
= 1(gmro)ro ∥(gmro)ro
2
= 1(gmro)ro 3
(c) When vo is short-circuited to ground, Rin2 becomes equal to 1/gm3. This resistance will be much smaller than the two other resistances between the drain of Q1 and ground, namely,
Ro = (gm3ro3) (gm2ro2) ro1
Ro1 = ro and Ro2 = ro. Thus the signal current in the drain of Q1, gm1vi will mostly flow into 1/gm3, that is, into the source of Q3 and out of the drain of Q3 to ground. Thus, the output short-circuit current will be equal to gm1vi; thus the short-circuit transconductance Gm will be
gmro = |VA|/VT β
Chapter 8–27
rπ = gm Thus,
Gm=gm1 Q.E.D. (d) vo = −gm1Ro
|VA| Iro rπ IRo=V r+r
T o π = |VA| |VA| rπ
vi
=−g ×1(gr)r
VT ro+rπ =|VA| |VA|
m 3moo
1 rπ
VT1+ro |VA| |VA|
= −3(gmro)2 For
=V1
T 1+βgmro
gm =2mA/V and vo=−1(30)2=−300V/V
A0 =30
|VA| =VT
1
1 +11 |VA| βVT
vi 3 8.76
=
|VA| Q.E.D. (VT /|VA|) + (1/β)
VCC
VB4 Q4
VB3 Q3
For |VA| = 5 V and β = 50 we obtain
IRo = 5 = 200 V
(0.025/5) + (1/50)
I (mA)
0.1
0.5
1
Ro (k)
2000
400
200
Ro = (gm3ro3)(ro4 ∥ rπ3) I = 0.2 mA
gm3= I = 0.2 =8mA/V VT 0.025
ro3=ro4=VA = 5 =25k I 0.2
rπ3= β =50=6.25k gm3 8
Ro =(8×25)(25∥6.25) = 1 M
2
= −1(gmro) gmrorπ
Ro
8.78 Refer to Fig. 8.38. When all transistors have equal β and ro, and, since they conduct equal currents, they have equal gm, then
Ron = Rop = gmro(ro ∥ rπ )
Ro = Ron ∥Rop = 1(gmro)(ro ∥rπ)
2
Av =−gmRo
= −1(gmro)gm(ro ∥rπ)
2 rπ +ro
8.77 When Eq. (8.88) is applied to the case of identical pnp transistors, it becomes
Ro = (gmro)(ro ∥rπ) Now,
ro = |VA| I
= −1(gmro) 1
2 1+1
gm ro gm rπ
Substituting gmro = |VA| and gmrπ = β,
VT 1 |VA|/VT
Av = −2 (VT/|VA|)+(1/β)
For |VA| = 5 V and β = 50 we obtain
gm = I VT
Av =−1 5/0.025
2 (0.025/5) + (1/50)
=−4000V/V
8.79 The output resistance of the cascode amplifier (excluding the load) is
Ro =gmro(ro∥rπ)
Thus,
Av =−gm(Ro∥RL)
= −gm(Ro ∥ βro)
For|VA|=100V,β=50,andI=0.2mAwe obtain
gm = I = 0.2 =8mA/V VT 0.025
β 50
rπ=g =8=6.25k
m
ro = |VA| = 100 =500k
I 0.2
Ro = 8×500×(500∥6.25)
= 24, 691 k
Av =−8(24.7∥25)×103 =−99.4×103 ≃−105 V/V
8.80 (a) Refer to circuit in Fig. P8.80(a). gm1 = I = 0.1 =4mA/V
VT 0.025 gm2 =gm1 =4mA/V
β 100 rπ1=rπ2=g = 4 =25k
m
ro1 = ro2 = |VA| = 5 = 50 k
I 0.1 Rin =rπ1 =25k
Ro = gm2ro2(ro1 ∥ rπ2)
= (4 × 50)(50∥25) = 3.33 M
Avo =−gmRo
=−4×3.33×103 =−13,320V/V (b) Refer to the circuit in Fig. P8.80(b).
gm1 = I = 0.1 = 4 mA/V VT 0.025
gm2 = 2ID2 = 2I = 2 × 0.1 = 1 mA/V VOV VOV 0.2
rπ1 = β = 100 = 25 k gm1 4
ro1=|VA|= 5 =50k I 0.1
ro2 = |VA| = 5 =50k I 0.1
Rin =rπ1 =25k
Ro = gm2ro2ro1
= 1×50×50 = 2.5 M
Avo =−gm1Ro
=−4×2.5×103 =−10,000V/V
(c) Refer to the circuit in Fig. P8.80(c).
2ID 2I 2 × 0.1 gm1=gm2=|VOV|=|VOV|= 0.2 =
1 mA/V
ro1 =ro2 =|VA|=|VA|= 5 =50k
ID I 0.1
Rin = ∞
Ro = gm2ro2ro1
= 1×50×50 = 2.5 M
Avo =−gm1Ro =−1×2.5×183 =−2500V/V (d) Refer to the circuit in Fig. P8.80(c).
gm1 = 2ID = 2I = 2×0.1 =1mA/V |VOV | |VOV | 0.2
gm2= I = 0.1 =4mA/V VT 0.025
ro1=|VA|= 5 =50k I 0.1
ro2 =|VA|= 5 =50k I 0.1
rπ2 = β = 100 =25k gm2 4
Rin=∞
Ro = (gm2ro2)(ro1 ∥rπ2)
= 4 × 50(50 ∥ 25)
= 3.33 M
Avo =−gm1Ro
=−1×3.33×106 =−3330V/V
Comment: The highest voltage gain (13,320 V/V) is obtained in circuit (a). However, the input resistance is only 25 k. Of the two circuits with infinite input resistance (c and d), the circuit in (d) has the higher voltage gain. Observe that combining MOSFETs with BJTs results in circuits superior to those with exclusively MOSFETs or BJTs.
8.81 (a) Refer to the circuit in Fig. P8.81(a).
g = 2μC W I m1 n ox L D
=√2×0.4×25×0.1 =1.41mA/V
Chapter 8–28
ro1 = VA = 1.8 = 18 k ID 0.1
gm2= I = 0.1 =4mA/V VT 0.025
gm2 = gm3 = 2ID2,3 = 2×0.2 = 1.6 mA/V VOV 2,3 0.25
ro2 = ro3 = VA = 10 = 50 k ID 0.2
Chapter 8–29
ro2 = VA = 1.8 = 18 k Ro = gm3ro3ro2 I 0.1
rπ2= β =125=31.25k gm2 4
Gm = gm1 = 1.41 mA/V
= 1.6×50×50 = 4 M
8.83
Ro = gm2ro2(ro1 ∥ rπ2)
= 4 × 18 × (18 ∥ 31.25) = 822.3 k
Avo = −GmRo = −1.41 × 822.3 = −1159 V/V I (b) Refer to circuit in Fig. P8.81(b).
gm1 =gm2 =√2×0.4×25×0.1
= 1.41 mA/V
ro1 =ro2 = VA = 1.8 =18k I 0.1
Gm = gm1 = 1.41 mA/V
Ro = gm2ro2ro1
= 1.41×18×18 = 457 k
Avo =−GmRo =−1.41×457=−644V/V
We observe that the circuit with a cascode transistor provides higher gain.
8.82 Refer to Fig. 8.39. I =I (W/L)2
REF
(gm3ro3) (gm2ro2)ro1
IO
(gm2 ro2)ro1 ro1
Q6
Q5
Q4
From the figure we see that Ro = (gm3ro3)(gm2ro2)ro1
Q3
Q2
Q1
O REF (W/L)1
= 2040/1 = 200 μA 8.84 Refer to Eq. (8.95),
4/1
1 W Ro = β3ro3/2
I=μCV2 D1 2 n ox L OV1
1 where
20 = 1 × 160 × 4 × V 2
2 1OV1
⇒VOV1 =0.25V
VG2 = VGS1 = Vt +VOV1 = 0.6+0.25 = 0.85 V
V =V OV4 OV1
Thus,
VGS4 =VGS1 =0.85V
VG3 = 0.85+0.85 = 1.7 V
The lowest voltage at the output while Q3 remains in saturation is
VOmin = VG3 − Vt3 = 1.7 − 0.6 = 1.1 V
VA 100 V
ro3 = I = 1 mA = 100 k
Thus,
Ro= 2 =5M
100×100
△IO = △VO = 10 V = 2 μA
Ro 5 M △IO = 2μA =0.002
IO 1 mA
or0.2%
8.85 (a) IO1 = IO2 = 1 IREF
21+2 β2
(b)
IREF
0.7 mA
Q1
IO1 IO2 Q3Q4 Q5
124
Q1
R = 1.1 + 2.5 = 36 k 0.1
VOmax is limited by Q3 saturating. Thus VOmax = VE3 − VECsat
= 1.8−0.3 = 1.5 V
8.87 Replacing each of the transistors in the Wilson mirror of Fig. 8.40 with its T model while neglecting ro results in the circuit shown below.
Chapter 8–30
IO3
aie3 ie3
re3 1
ie1
re1
Note that the diode-connected transistor Q1 reduces to a resistance re1. To determine Rin, we have applied a test voltage vx. In the following we analyze the circuit to find ix and hence Rin, as
vx Rin ≡ ix
Note that all three transistors are operating at equal emitter currents, approximately equal to IREF. Thus
re1 =re2 =re3 = VT IREF
Analysis of the circuit proceeds as follows. Since re1 = re2, we obtain
ie2 = ie1 (1) Node equation at node 1:
ie3 +αie2 = ie1 +ie2
Using Eq. (1) yields
ie3 = (2 − α)ie1 (2) Node equation at node 2:
ix =αie2 +(1−α)ie3
Using Eqs. (1) and (2) yields
ix =ie1[α+(1−α)(2−α)]
ix =ie1[2−2α+α2] (3)
ix
vx Rin
2
(1a) ie3
ie2
aie2
VEE
The figure shows the required circuit. Observe that the output transistor is split into three transistors having base–emitter junctions with area ratio 1:2:4. Thus
= 0.0999 mA
re2
IO1 = 0.1 1 + 2
= 0.1 1 + 2
β2 IO2 = 0.2
502
= 0.1998 mA
1 + 2 502
0.4 IO4 = 2
1 + 502
= 0.3997 mA
8.86
1.1 V R
2.5 V
2.5 V
1.8 V
Q2
Q1
Q3
IO
0.1 mA
VO
Finally, vx can be expressed as the sum of the voltages across re3 and re1,
vx =ie3re +ie1re
Using Eq. (2) yields
vx =ie1re(3−α)
Dividing Eq. (4) by Eq. (3) yields
R =vx =r 3−α
(4)
of Q4 would appear in series with the gate of Q3 and thus carries zero current. Thus including Q4 has no effect on the value of Ro, which can be found from Eq. (8.96):
Ro = gm3ro3ro2 where
gm3 = 2ID = 2×0.18 =1.2mA/V
in i x
e 2 − 2α + α2
VOV ro2 =ro3 = I
REF
0.3
= 0.18 =100k
Chapter 8–31
VA
18
For α ≃ 1,
Rin = 2re = 2 VT
Thus,
Ro = 1.2×100×100 = 12 M (f) For △VO = 1 V, we obtain
△IO =△VO = 1V =0.08μA Ro 12 M
IO = 0.04% IO
8.89 Replacing each of the three transistors in the Wilson current mirror in Fig. 8.41(a) with its
T model results in the circuit in the figure.
Q.E.D. Thus, for IREF = 0.2 mA,
Rin =250
8.88 Refer to circuit in Fig. 8.41(a).
(a) Each of the three transistors is operating at ID = IREF. Thus
IREF
1 W I=μCV2
REF 2 n ox L OV 180 = 1 × 400 × 10 × V 2
2 OV ⇒VOV =0.3V
ix
i3 i3
1 gm3
VG3 = Vtn + VOV = 0.5 + 0.3 = 0.8 V
(b) Q1 is operating at VDS = VGS = 0.8 V Q2 is operating at VDS = 2VGS = 1.6 V Thus,
IREF −IO = △VDS
where
ro=VA =18=100k IREF 0.18
IREF −IO = 0.8 =0.008mA=8μA 100
IO = 180 − 8 = 172 μA
(c) Refer to Fig. 8.41(c). Since Q and Q are
2
i2
vx 1
ro 11
i2 i1 gm2 gm1
Rin
Here, we have applied a test voltage vx to
determine Rin,
Rin ≡ vx 12 ix
now operating at equal VDS , we estimate IO = IREF = 180 μA.
(d) The minimum allowable VO is the value at which Q3 leaves the saturation region:
VOmin = VG3 − Vt
=VGS3 +VGS1 −Vt
= 0.8+0.8−0.5 = 1.1 V
(e) Diode-connected transistor Q4 has an incremental resistance 1/gm4. Reference to Fig. 8.41(b) indicates that the incremental resistance
Since all three transistors are identical and are operating at the same ID,
gm1 = gm2 = gm3
Now from the figure we see that i1 = i2
and
i2 + i3 = i2 + i1
Thus
i3 =i1 =i2
A node equation at node 2 gives ix + i3 = i2 + i3
Thus
ix = i2
The voltage vx can be expressed as the sum of the voltages across 1/gm3 and 1/gm1:
vx =(i3/gm3)+(i1/gm1)
Substituting i3 = i2 and i1 = i2, gm1 = gm3 = gm,
rπ2 = β = 200 = 250 k gm 0.8
Rout =(2.9∥250)+2500+0.8×2500×(2.9∥250)
= 8.2 M
Chapter 8–32
A 5-V change in VO gives rise to 5
and
vx =2i2/gm Buti2 =ix;thus vx =2ix/gm and thus
Rin = 2 gm
8.90
IREF
200 A
Q1
△IO = 7.1 = 0.7 μA 8.91 Refer to Fig. 8.42.
(a) To obtain a current transfer ratio of 0.8 (i.e., IO/IREF =0.8andIO =80μA),wewrite
I IORE=VTln REF
Q.E.D.
VBE1
100 ⇒ RE = 69.7
IO 0.08RE = 0.025 ln 80
VBE2
Q2
Rout
IO 20A
RE
gm2 = 0.08 = 3.2 mA 0.025
ro2 = 50 =625k 0.08
rπ2 =∞(becauseβ=∞) Rout = RE + ro2 + gm2ro2RE
= 0.069+625+3.2×625×0.0697 = 764.5 k
Relative to the value of ro2,
Rout = 1.22 ro2
(b) To obtain IO /IREF = 0.1, that is, IO = 10 μA, we write
100 0.01 RE = VT ln 10
⇒RE =5.76k
gm2 = 0.01 = 0.4 mA/V
0.025
ro2 = 50 =5000k 0.01
rπ2 =∞
Rout = RE + ro2 + gm2ro2RE
= 5.76+5000+0.4×5000×5.76
= 16.5 M
Compared to r , o2
Rout = 16.5 =3.3 ro2 5
(a) Assuming β is high so that we can neglect base currents,
I IORE =VT ln REF
IO
Substituting IO = 20 μA and IREF = 200 μA
results in
0.02 RE = 0.025 ln 20
200
(b) Rout = (RE ∥ rπ2) + ro2 + gm2ro2(RE ∥ rπ2)
⇒RE =2.88k where
gm2 = 0.02 = 0.8 mA/V 0.025
ro2 = VA = 50 =2500k IO 0.02
(c) To obtain IO /IREF = 0.01, that is, IO = 1 μA, 8.94
we write
G
100 gm2 = 0.001 = 0.04 mA/V
Chapter 8–33
0.001 RE = 0.025 ln 1
S
⇒ RE = 115 k vgs ix
0.025
r = 50 =50×103k r
vx vx
o2 0.001 vgs vbs o3 Rout = 115+50×103 +0.04×50×103 ×115 = 280 M
Relative to the value of ro2,
gmvgs ro1
The figure shows the equivalent circuit of the source follower prepared for finding Ro. Observe that we have set vi = 0 and applied a test voltage vx. We note that
gmbvbs B
Ro ix
Rout =280=5.6 ro2 50
8.92 (a) Refer to the circuit in Fig. P8.92. Neglecting the base currents, we see that all three transistors are operating at IC = 10 μA, and thus
1 mA VBE1 =VBE2 =VBE3 =0.7−0.025ln 10μA
= 0.585 V
From the circuit we see that the voltage across R
isVBE =0.585V,thus IOR = VBE
R = 0.585 = 58.5 k 0.01
(b) gm3 = 0.01 = 0.4 mA/V 0.025
ro3 = 40 =4000k 0.01
rπ3 = β = 100 =250k gm3 0.4
Rout =(R∥rπ3)+ro3 +gm3ro3(R∥rπ3)
= (58.5 ∥ 250)+4000+0.4×4000×(58.5 ∥ 250) = 79.9 M
8.93 Refer to the circuit in Fig. P8.93. Since Q1 and Q2 are matched and conducting equal currents I, their VGS values will be equal. Thus from the loop Q1, Q6, R, and Q2, we see that
IR=VEB6 I
1 mA 0.2R = 0.7 − 0.025 ln 0.2 mA
⇒ R = 3.3 k
vgs = vbs = −vx
and
ix =−gmbvbs + vx −gmvgs + vx ro1 ro3
Thus,
ix =gmbvx + vx +gmvx + vx ro1 ro3
from which we obtain Ro≡vx =ro1∥ro3∥ 1
(1)
Q.E.D.
ix gm + gmb
8.95 The dc level shift provided by a source
follower is equal to its VGS . Thus, to obtain a dc levelshiftof0.9V,wewrite
VGS =0.9V=Vt +VOV
⇒ VOV = 0.9−0.6 = 0.3 V
To obtain the required bias current, we use
1 W I=I=μC V2
D 2 n ox L OV 1 20 2
= 2 × 0.2 × 0.5 × 0.3
=VT ln I S
I =0.36mA=360μA
gm = 2ID = 2×0.36 =2.4mA/V VOV 0.3
gmb =χgm =0.2×2.4=0.48mA/V
ro = VA = VA′L = 20×0.5 =27.8k
ID ID 0.36
To determine Av o , we note [refer to Fig. 8.45(b)] that the total effective resistance between the MOSFET source terminal and ground is
Q.E.D. NowtoobtainI =0.2mA,wewrite
ro1 ∥ro3 ∥ 1 . Denoting this resistance R, we gmb
have R=ro∥ro∥ 1
gmb
= 27.8∥27.8∥ 1 0.48
= 1.81 k
Thus, the open-circuit voltage gain is
(a) Rin2 = rπ2 = 12.5 k
Rin = (β1 + 1)[re1 + (rπ2 ∥ ro1)] = 101[0.125 + (12.5 ∥ 250)]
= 1.215 M
Chapter 8–34
vb1 vsig ve1 vb1
= =
Rin = Rin + Rsig
1.215 = 0.71 V/V 1.215 + 0.5
Avo= R R+1
gm
=0.99V/V
vo =−gm2ro2=−8×250=−2000V/V
rπ2∥ro1 (rπ2 ∥ro1)+re1
vb1
Gv = vo = 0.71×0.99×−2000 = −1405 V/V
gm = 80 mA/V re = 0.0125 k rπ = 1.25 k ro =25k
Rin2 =rπ2 =1.25k
Rin = 101[0.0125 + (1.25 ∥ 25)] = 121.5 k Thus, Rin has been reduced by a factor of 10.
vb1 = 121.5 vsig 121.5 + 500
= 0.2 V/V (considerably reduced) ve1 = (1.25 ∥ 25)
vb1 (1.25 ∥ 25) + 0.0125
1.81 1.81 + 2.4
= 0.81 V/V
vsig
(b) Increasing the bias current by a factor of 10 (i.e., to 2 mA) results in
=
Ro = R// 1
1
gm
= 1.81 k// = 0.339 k
1
2.4 mA/V
When a load resistance of 2 k is connected to the output, the total resistance between the output node and ground become R∥RL = 1.81∥2 = 0.95 k. Thus, the voltage gain becomes
0.95
0.95+ 1 2.4
= 0.7 V/V
Av =
8.96
vsig
5 V Rsig 500 k
Q1
200 A
Rin
200 A vo
= 0.99 V/V (unchanged) vo =−gm2ro =−80×25
vb1
= −2000 V/V (unchanged)
Q2
Gv = vo =0.2×0.99×−2000=−396V/V vsig
which has been reduced by a factor of 3.5! All this reduction in gain is a result of the reduction in Rin.
8.97
5 V
3 k
0.7 VGS 0
Each of Q1 and Q2 is operating at an IC approximately equal to 200 μA. Thus for both devices,
gm = 0.2 = 8 mA/V 0.025
r ≃ 1 =0.125k e gm
β 100
rπ=g = 8 =12.5k
m
ro = VA = 50 = 250 k IC 0.2
VGS
0.7 0.1 6.8 mA
Q1 0.1 mA 0.7 V
0
6.8 k Figure 1
Q
Rin2 r2
RG 10 M
2
(a) From Fig. 1 we see that ID1 ≃ 0.1 mA/V
But
vo = 487 vsig 487 + 500
× −19.5
D1 2 n ox L OV 0.1 = 1 × 2 × V 2
Chapter 8–35
1 W
I = μC V2
= −9.6 V/V
(e) The suggested configuration, shown partially
inFig.3,willhave
10 M 10 M 2OV vi vo
⇒VOV =0.316V
VGS =Vt +VOV =1.316V
Thus,
VC2 = VG2 = 0.7+VGS = 2.016 V
IC2 = VCC −VC2 = 5−2.016 ≃1mA 3 k 3
(b) gm1 = 2ID1 = 2×0.1 =0.632mA/V VOV 0.316
Figure 3
noeffectonthedcbiasofeachtransistor. However, it will have a profound effect on Rin, as Rin nowis10M,and
vo = 10 × −19.5 = −18.6 V/V vsig 10+0.5
This is nearly double the value we had before! 8.98 From Fig. P8.98 we see that
gm2 = IC2 = 1mA =40mA/V VT 0.025
rπ2= β =200=5k gm2 40
(c) NeglectingRG,wecanwrite vb2 = rπ2∥6.8k
vi (rπ2∥6.8k)+ 1 gm1
IE2=10mA
IE1 = IE2 ≃ 10 =0.1mA
= 0.65 V/V
vo =−gm2(3∥1)
β2 + 1 100
re2 = VT = 25mV =2.5
vb2
= −40 × 3 = −30 V/V
IE2 10 mA
re1 = VT = 25mV =250
IE1 0.1 mA
The Darlington follower circuit prepared for
small-signal analysis is shown in the figure.
Rsig 100 k
Q1
4
vo = 0.65 × −30 = −19.5 V/V
vi (d)
vi
RG
ii
Avvi
Figure 2 FromFig.2wecanfindii as
Q2 vi−Avvi R
ii= R G
= vi + 19.4 vi RG
Thus,
Rin≡vi = RG =10M=487k
ii 20.5 20.5
Thus the overall voltage gain becomes
vo=Rin ×Av vsig Rin + Rsig
vsig out
RL 1 k
Rin
Rin =(β+1)[re1 +(β2 +1)(re2 +RL)] = 101[0.25 + (101)(0.0025 + 1)]
= 10.25 M
Rout = re2 + re1 + Rsig/(β1 + 1) β2 + 1
8.100
Rsig
Chapter 8–36
250 + 100 × 103 = 2.5 + 101
101 With RL removed,
Gvo=vo =1 vsig
With RL connected,
G=vo=G RL
v v voR+R
= 14.8
RL
Q1 11
Q2
gm1 gm2
= 1 × 8.99
= 0.985
voltage gain as
sig
1
1 + 0.0148
L out
vs
From the figure we can determine the overall
Gv = vo vsig
=
Total resistance in the drain Total resistance in the sources
= 1gmRL gm =gm1 =gm2 =5mA/V
= RL
1+1 2
Rsig 10 k
Q1
Q2
1
Gv =2×5×10=25V/V
8.101 Refer to Fig. P8.101. All transistors are operating at IE = 0.5 mA. Thus,
re=VT =25mV=50 IE 0.5 mA
(a) Refer to Fig. P8.101(a).
vo = − α × Total resistance in collector
vsig Total resistance in emitter
= −α × 10 k 10 k + re
β+1
RL 10 k
gm1 gm2 where
vsig
re1
re2
The figure shows the circuit prepared for signal analysis.
Gv = vo vsig
= α × Total resistance in collectors Total resistance in emitters
=
αRL
Rsig +r +r
β+1 e1 e2 where
For
α= β = 100 =0.99
α≃1
re1=re2=I =0.5mA=50
= 50.2 V/V
β+1 101
Gv = −0.99×10 =−66.4V/V
VT 25mV E
10+0.05 101
Gv = 10
(b) Refer to Fig. P8.101(b).
i = vsig = vsig
10 +0.05+0.05 101
b1 10+(β +1)re1
10+101×0.05
ic1 = βib1 = 100 vsig ic1 = β1ib1 = 100 vsig 10+101×0.05 10+101×0.05
Chapter 8–37
ic2 =αic1 = 0.99×100vsig 10+101×0.05
ie2 = ic1
ic2 =αie2 =αic1 = 0.99×100vsig
vo =−ic2 ×10
Gv ≡ vo =−10×0.99×100 =−65.8V/V
10+101×0.05 vo = ic2 ×10 = 0.99×100×10 vsig
vsig 10 + 101 × 0.05 (c) Refer to Fig. P8.101(c).
Thus,
Gv = vo vsig
(f)
10+101×0.05
= 0.99×100×10 = 65.8 V/V
vo α × Total resistance in collector
10 + 101 × 0.05
ic2
= Total resistance in emitters 10 +2r 10 +2×0.05
Gv = v
= 0.99×10 = 0.99×10
sig
(d) Refer to Fig. P8.101(d).
Rin (at the base of Q1) = (β1 + 1)[re1 + rπ2]
where
re1 =50
rπ2 =(β+1)re2 =101×50=5.05k
Thus,
Rin = 101(0.05 + 5.05) = 515 k
vb1 vsig
vb2
vo 10 k
β+1 e 101 = 49.7 V/V
Q2
10 k
ie1 ie2 Q1
vsig
ie1 = ie2 =
vsig
10 +r +r
Rin = Rin + Rsig
515 515 + 10
β1+1 e1 e2 vsig
=
= r +r
= 0.98 V/V = 5.05+0.05 = 0.98 V/V
= 10
101 + 0.05 + 0.05
rπ 2
π2 e1
5.05
v vo
b1
=−gm2 ×10k
= −20 × 10 = −200 V/V
ic2 = αie2 = 0.99 vsig
10 +0.05+0.05
vb2
Gv = vo =0.98×0.98×−200=−194V/V
vsig
(e) Refer to Fig. P8.101(e).
i = vsig = vsig
b1 10+(β +1)re1 10+101×0.05
101 vo =ic2 ×10k=
Thus,
0.99×10vsig 10 +0.05+0.05
101
Gv = vo =49.7V/V vsig