41 2 0
38 1
8 252 396 301 347 1 0
8 318 396 367 347 1 0
22 258 348 424 328 0 \NUL
Read Register 1 Address
8 432 396 481 347 1 0
8 498 396 547 347 1 0
22 438 348 604 328 0 \NUL
Read Register 2 Address
20 720 414 787 395 0
wadr_0
20 654 414 721 395 0
wadr_1
8 606 396 655 347 1 0
8 672 396 721 347 1 0
22 612 348 767 328 0 \NUL
Write Register Address
20 480 414 547 395 0
adr2_1
20 546 414 613 395 0
adr2_0
20 366 414 433 395 0
adr1_0
20 300 414 367 395 0
adr1_1
19 166 108 233 89 0
reg0_2
19 154 84 221 65 0
reg0_3
19 190 156 257 137 0
reg0_0
19 178 132 245 113 0
reg0_1
11 258 108 285 10 0 1
22 144 36 255 16 0 \NUL
Register 0 Value
19 322 108 389 89 0
reg1_2
19 310 84 377 65 0
reg1_3
19 346 156 413 137 0
reg1_0
19 334 132 401 113 0
reg1_1
11 414 108 441 10 0 1
22 300 36 411 16 0 \NUL
Register 1 Value
19 478 108 545 89 0
reg2_2
19 466 84 533 65 0
reg2_3
19 502 156 569 137 0
reg2_0
19 490 132 557 113 0
reg2_1
11 570 108 597 10 0 1
22 456 36 567 16 0 \NUL
Register 2 Value
19 634 108 701 89 0
reg3_2
19 622 84 689 65 0
reg3_3
19 658 156 725 137 0
reg3_0
19 646 132 713 113 0
reg3_1
11 726 108 753 10 0 1
22 612 36 723 16 0 \NUL
Register 3 Value
19 640 264 707 245 0
alu_2
19 628 240 695 221 0
alu_3
19 664 312 731 293 0
alu_0
19 652 288 719 269 0
alu_1
11 732 264 759 166 0 1
22 648 192 724 172 0 \NUL
ALU Output
25 12 528 119 432
8 12 396 61 347 1 0
8 6 288 55 239 1 1
8 6 192 55 143 1 1
20 66 414 133 395 0
sel
20 60 210 127 191 0
clear
20 150 510 217 491 0
kpad_3
20 138 534 205 515 0
kpad_2
20 132 558 199 539 0
kpad_1
20 120 582 187 563 0
kpad_0
19 328 264 395 245 0
in1_2
19 316 240 383 221 0
in1_3
19 352 312 419 293 0
in1_0
19 340 288 407 269 0
in1_1
11 420 264 447 166 0 1
22 336 192 414 172 0 \NUL
ALU Input 1
22 12 78 52 58 0 \NUL
Lab 2
22 12 30 102 10 0 \NUL
Slug, Sammy
22 12 54 52 34 0 \NUL
sslug
19 166 264 233 245 0
kpad_2
19 154 240 221 221 0
kpad_3
19 190 312 257 293 0
kpad_0
19 178 288 245 269 0
kpad_1
11 258 264 285 166 0 1
22 150 192 249 172 0 \NUL
Keypad Output
22 12 144 117 124 0 \NUL
Clear Registers
22 18 324 100 304 0 \NUL
Store Select
20 60 294 127 275 0
update
22 12 240 121 220 0 \NUL
Update Register
19 484 264 551 245 0
in2_2
19 472 240 539 221 0
in2_3
19 508 312 575 293 0
in2_0
19 496 288 563 269 0
in2_1
11 576 264 603 166 0 1
22 492 192 570 172 0 \NUL
ALU Input 2
22 18 348 230 328 0 \NUL
0 = Keypad input, 1 = ALU result
22 12 102 149 82 0 \NUL
CSE 12, Spring 2021
22 228 450 478 430 0 \NUL
Select clear to initialize registers to 0.
22 228 474 557 454 0 \NUL
Select store select to choose which value to store.
22 228 498 508 478 0 \NUL
Choose read and write register addresses.
22 228 522 727 502 0 \NUL
Read addresses = reg sources of ALU inputs, Write address = reg to save to
22 228 546 480 526 0 \NUL
Press update to save value to register
22 228 594 668 574 0 \NUL
You are only permitted to modify the header comment on this page.
1 652 371 655 404
1 718 371 721 404
1 478 371 481 404
1 544 371 547 404
1 364 371 367 404
1 298 371 301 404
1 218 74 259 74
1 259 80 230 98
1 259 86 242 122
1 259 92 254 146
1 374 74 415 74
1 415 80 386 98
1 415 86 398 122
1 415 92 410 146
1 530 74 571 74
1 571 80 542 98
1 571 86 554 122
1 571 92 566 146
1 686 74 727 74
1 727 80 698 98
1 727 86 710 122
1 727 92 722 146
1 692 230 733 230
1 733 236 704 254
1 733 242 716 278
1 733 248 728 302
1 61 200 52 167
1 67 404 58 371
1 380 230 421 230
1 421 236 392 254
1 421 242 404 278
1 421 248 416 302
1 151 500 116 500
1 139 524 116 506
1 133 548 116 512
1 121 572 116 518
1 218 230 259 230
1 259 236 230 254
1 259 242 242 278
1 259 248 254 302
1 61 284 52 263
1 536 230 577 230
1 577 236 548 254
1 577 242 560 278
1 577 248 572 302
38 2
19 22 426 89 407 0
wadr_1
19 22 408 89 389 0
wadr_0
19 22 354 89 335 0
adr2_1
19 22 336 89 317 0
adr2_0
19 22 294 89 275 0
adr1_1
19 22 276 89 257 0
adr1_0
19 22 228 89 209 0
sel
19 22 210 89 191 0
update
19 22 192 89 173 0
clear
20 690 30 757 11 0
reg0_3
20 690 48 757 29 0
reg0_2
20 690 66 757 47 0
reg0_1
20 690 84 757 65 0
reg0_0
20 690 114 757 95 0
reg1_3
20 690 132 757 113 0
reg1_2
20 690 150 757 131 0
reg1_1
20 690 168 757 149 0
reg1_0
20 690 198 757 179 0
reg2_3
20 690 216 757 197 0
reg2_2
20 690 234 757 215 0
reg2_1
20 690 252 757 233 0
reg2_0
20 690 282 757 263 0
reg3_3
20 690 300 757 281 0
reg3_2
20 690 318 757 299 0
reg3_1
20 690 336 757 317 0
reg3_0
20 690 366 757 347 0
in1_3
20 690 384 757 365 0
in1_2
20 690 402 757 383 0
in1_1
20 690 420 757 401 0
in1_0
20 690 450 757 431 0
in2_3
20 690 468 757 449 0
in2_2
20 690 486 757 467 0
in2_1
20 690 504 757 485 0
in2_0
20 690 534 757 515 0
alu_3
20 690 552 757 533 0
alu_2
20 690 570 757 551 0
alu_1
20 690 588 757 569 0
alu_0
22 294 42 484 22 0 \NUL
Placeholder signal/recievers
22 18 480 388 460 0 \NUL
These are only present so circuit simulates without error
22 18 504 290 484 0 \NUL
Remove these once logic is implemented
22 18 528 266 508 0 \NUL
You are permitted to modify this page
22 12 78 52 58 0 \NUL
Lab 2
22 12 30 102 10 0 \NUL
Slug, Sammy
22 12 54 52 34 0 \NUL
sslug
22 12 102 149 82 0 \NUL
CSE 12, Spring 2021
38 3
22 12 78 52 58 0 \NUL
Lab 2
22 12 30 102 10 0 \NUL
Slug, Sammy
22 12 54 52 34 0 \NUL
sslug
22 12 102 149 82 0 \NUL
CSE 12, Spring 2021
38 4
22 12 78 52 58 0 \NUL
Lab 2
22 12 30 102 10 0 \NUL
Slug, Sammy
22 12 54 52 34 0 \NUL
sslug
22 12 102 149 82 0 \NUL
CSE 12, Spring 2021
38 5
22 12 78 52 58 0 \NUL
Lab 2
22 12 30 102 10 0 \NUL
Slug, Sammy
22 12 54 52 34 0 \NUL
sslug
22 12 102 149 82 0 \NUL
CSE 12, Spring 2021
39 16777215
47 0
40 1 6 6
50 800 600
51 0 100
30
System
16
700
0
0
0
0
0
34