DT131B
Embedded Systems Programming
Lecture 5-6: Embedded Systems Hardware
Dawit Mengistu (dawit.mengistu@hkr.se)
Review: Embedded Systems Arichtecture
Display
Microcontroller (Processing System)
A/D-converters Input Interface
Output Interface
Actuators
Sensors
Temp, pressure, etc
Environment
2
Microcontroller Overview
Actuator Sensor
Processor
Control (Output)
Motor Speed /Warning Light
Observe (Input)
Temperature Transducer
Memory
3
System Bus
Embedded System Architecture
Memory
Program
Data
I/O Unit
Comm I/O 123
…
ADC 12 …
Digital I/O 1
2
3 …
Timers
Remote
Peripherals
Micro controller
Comm Unit (BT, WiFi, LAN…)
Sensors 123
…
CPU
Human Interface
Display
Actuators 123
…
Microcontrollers
• Control‐dominant applications
– supports process scheduling and synchronization – preemption (interrupt),context switch
– short latency times
• Low power consumption
• Peripheral units often integrated • Suited for real‐time applications
Other types of processors: DSP, ASIC, SOC…
6
Review: Microcontroller Components
CPU
• Memory
• Input‐output units
In the first few lectures of this course, we studied the CPU and its organization.
We now look at the other components.
•
7
Memory Unit (Introduction)
Memory Map
9
Semiconductor Memory
• RAM
– Misnamed as all semiconductor memory is
random access
– Read/Write
– Volatile
– Temporary storage
– Static or dynamic
10
Memory Cell Operation
11
Dynamic RAM
• Bitsstoredaschargeincapacitors
• Chargesleak
• Needrefreshingevenwhenpowered
• Simplerconstruction
• Smallerperbit
• Less expensive
• Needrefreshcircuits
• Slower
• Mainmemory
• Essentiallyanalogue
– Level of charge determines value 12
DRAM Operation
• Address line active when bit read or written – Transistorswitchclosed(currentflows)
• Write
– Voltagetobitline
• Highfor1lowfor0
– Thensignaladdressline
• Transfers charge to capacitor
• Read
– Addresslineselected • transistor turns on
– Chargefromcapacitorfedviabitlinetosenseamplifier • Compares with reference value to determine 0 or 1
– Capacitor charge must be restored
13
Static RAM
• Bitsstoredason/offswitches
• Nochargestoleak
• Norefreshingneededwhenpowered
• Doesnotneedrefreshcircuits
• Morecomplexconstruction
• Largerperbit
• Moreexpensive
• Faster
• Cache
• Digital
– Uses flip‐flops
14
SRAM v DRAM Summary
• Bothvolatile
– Power needed to preserve data
• Dynamiccell
– Simpler to build, smaller
– More dense
– Less expensive
– Needs refresh
– Larger memory units
• Static
– Faster
– Cache
15
Read Only Memory (ROM)
• Permanent storage – Nonvolatile
• Used often in microprogramming (see later)
• Also stores
– Library subroutines
– Systems programs (BIOS) – Function tables
16
Types of ROM
• Writtenduringmanufacture – Very expensive for small runs
• Programmable(once) – PROM
– Needs special equipment to program • Read“mostly”
– Erasable Programmable (EPROM) • ErasedbyUV
– Electrically Erasable (EEPROM)
• Takes much longer to write than read
– Flash memory
• Erasewholememoryelectrically
17
Organisation in Detail
• A16Mbitchipcanbeorganisedas1Mof16bit words
• Abitperchipsystemhas16lotsof1Mbitchipwith bit 1 of each word in chip 1 and so on
• A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array
– Reduces number of address pins
• Multiplex row address and column address
• 11 pins to address (211=2048)
• Addingonemorepindoublesrangeofvaluessox4capacity
18
Memory Organization
19
Packaging
20
Error Correction
• Hard Failure
– Permanent defect
• Soft Error
– Random, non‐destructive
– No permanent damage to memory
• Detected using Hamming error correcting code
21
Memory Types Summary
Memory Type
Category
Erasure
Write Mechanism
Volatility
Random-access memory (RAM)
Read-write memory
Electrically, byte-level
Electrically
Volatile
Read-only memory (ROM)
Read-only memory
Not possible
Masks
Nonvolatile
Programmable ROM (PROM)
Electrically
Erasable PROM (EPROM)
Read-mostly memory
UV light, chip-level
Electrically Erasable PROM (EEPROM)
Electrically, byte-level
Flash memory
Electrically, block-level
Input Output (I/O) Unit (Introduciton)
23
I/O Modules: Functions
• Control&Timing
• CPUCommunication
• DeviceCommunication • DataBuffering
• ErrorDetection
24
I/O Modules: Challenges
• Wide variety of peripherals
– Delivering different amounts of data – At different speeds
– In different formats
• All slower than CPU and RAM
25
• Human readable/writable – Screen, printer, keyboard
• Machine readable/writable – Monitoring and control
• Communication
– Modem
– Network Interface Card (NIC)
External Devices
26
Addressing I/O Devices
• For programmed I/O, data transfer is very like memory access (CPU viewpoint)
• Each device given unique identifier
• CPU commands contain identifier (address)
27
I/O Mapping
• Memory mapped I/O
– Devicesandmemoryshareanaddressspace
– I/Olooksjustlikememoryread/write – NospecialcommandsforI/O
• Large selection of memory access commands available
• Port mapped (Isolated) I/O – Separateaddressspaces
– NeedI/Oormemoryselectlines
– Supportforlimited,specialcommandsforI/O
28
I/O Module Operation Steps
• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU
• Variations: Interrupt, DMA, etc. (more about this later)
29
I/O Module Details
30
I/O Module Decisions
• Hide or reveal device properties to CPU
• Support multiple or single device
• Control device functions or leave for CPU
• Also O/S decisions
– e.g. Unix treats everything it can as a file
31
Input Output Techniques
Transferring data between peripheral and processor can take place in one of the following ways:
• Programmed
• Interrupt Driven
• Direct Memory Access (DMA)
(More on these techniques later in the course!)
32
Communication with Many I/Os
SLAVE Status Regs Control Regs
Data Regs
MASTER
Processor
Issues:
MASTER is tied up in communication with device until I/O operation is done
No other work can be accomplished by MASTER
Typically one MASTER in system, but many I/O devices
Only really useful if devices are fast No time consuming context switches
data/address
I/O Polling (Busy-Wait)
Continuouspolling Periodic polling
Loop (until device ready) { Check device
} End-loop
33
Interface
device 1
Interrupt requests
Interrupt Based
Comm. with Many I/Os (cont’)
System Bus
device 2
device n
Interrupt Identification SW polling (check status
registers) HW polling
Interrupt Priority (in case multiple interrupts to be served)
L1 L2 .. Ln
Processor
L1, L2, … are interrupt request lines
34
Further Reading
• William Stallings, Computer Organization and Architecture 8th ed. (2010) ‐ Chapter 12