Embedded Systems Design Assignment Programmable Logic Integrated Circuits
Synchronous and Asynchronous Finite State Machine Implementation
1.0 Objectives
The primary objective of this assignment is to implement a sophisticated digital circuit on a programmable logic device, or associated simulator. Students will be required to implement a synchronous and an asynchronous finite state machine design using the Vivado design package. Modifications to the basic synchronous design will be required in order to allow the machine to be forced into the not-allowed states for testing purposes.
This assignment is designed to a minimum of fifty hours of student effort. It is suggested that the associated preparatory work takes the form of a familiarisation exercise with the Vivado software package, Verilog module entry, simulations and verification.
2.0 Learning Outcomes
Deliverables:
i) A completed design for a synchronous and an asynchronous finite state machine. The designs will be implemented in Verilog.
ii) Any additional circuitry required to force the finite state machines into not allowed states.
iii) Adequate simulation and verification of your designs.
iv) A comprehensive field note book showing the design decisions and testing methodologies. This must be written for the benefit of a junior engineer working for you and for a lawyer reviewing your work.
v) Students will demonstrate that they have been able to deal with a very complex software package typical of the technology that they may be exposed to after graduation.
What will be assessed:
i) The designs, with particular emphasis on adequate commenting on the different stages and any attempt to minimise the complexity of the system by careful routing of not- allowed states (for the synchronous implementation).
ii) A working programmable logic device including any extra internal circuitry that will allow the machine to be jammed into any of the not-allowed states.
iii) The adequacy of the field note book including preparatory work and evidence that the documentation is written up as the assignment progresses. What will a junior engineer think of you?
iv) The ability of the field note book to convey testing procedures including thorough verification of the performance of the machines under abnormal conditions. (Statements to the effect of “it worked” are not those of a professional engineer)
Finite State Machine Design – Programmable Logic Implementation. Page – 2
3.0 Activities
3.1 Assignment Specification – Stage 1
A synchronous finite state machine is to be designed which will give one output pulse equal in length to a clock cycle, after a pre-defined number of clock transitions. The finite state machine should be designed to count cyclically through a pre-defined series of states corresponding to standard binary notation whilst skipping ‘not allowed’ states (e.g. for a non-existent specification: S15, S8, S9, S5, S3, S1, S10, S14, S2, S11, etc. = {1111, 1000, 1001, 0101, 0011, 0001, 1010} etc.). The finite state machine is to re-synchronise within one clock pulse to an allowed state should the system enter a ‘not allowed’ state at switch-on time. The state into which the finite state machine re-synchronises should be chosen to minimise the complexity of the circuitry. In order to test the finite state machine, it is necessary to include a means of loading states into the finite state machine. For this assignment, both transition function logic and output function logic will be designed.
Inputs (Primary State Variables)
X (t) Y(t)
Y(t1)
Y(t) Z(t)
Outputs
Transition Function
Feedback Paths (Secondary state Variables)
Figure 1: Moore Model Finite State Machine
Each student in the cohort will be issued with a unique specification and your deliverables will be checked to ensure that your personal assignment criteria have been met. The unique specification will have been emailed to students, typically of the form:
‘Student ID: 999, Repetitive state order: 1, 15, 14, 8, 9, 4, 10, 7, 12, 2, 11, 5, 13.
Z active on state: 2. The last sentence provides the specification of the output logic.
3.2 Assignment – Stage 1
Design the synchronous finite state machine minimising the combinational logic. The state diagram should be designed in a manner that results in a circuit using the minimum number of gates inputs. Implement the synchronous finite state machine targeted at using a Nexys 4 board programed in Verilog.
The deliverables of this assignment require that you can demonstrate the counter recovering from a not-allowed state. For testing purposes the ‘JAM_ENABLE’ signal will be activated before a clock pulse. This will allow the data placed on the input lines JAM_A to JAM_D to be clocked onto the output pins.
The clock pulses should be derived from a suitable switch de-bounce circuit as shown in Figure 2. This will produce a pulse when the switches alternatively activate the set and reset inputs of the logic – the circuitry for this should be included internally as a separate asynchronous finite state machine design.
Test the finite state machine – don’t forget to check that the machine re-synchronises within one clock cycle for your not allowed states. Think very carefully about how you describe to another engineer a formal testing method that is precise and concise.
Finite State Machine Design – Programmable Logic Implementation. Page – 3
State Memory
Output Function
S
R
The first step is to define the pin connections for the signals that you will use. Please use the following to ease the demonstration burden on staff.
The Digilent Nexys 4 DDR has sixteen LEDs. These are connected to the Artix-7 integrated circuit in the following manner:
Figure 2 : De-bounced clock circuit
Qn Output
Original Digilent Net Name
Synchronous FSM Signal
Artix-7 I/O Pin Number
LED<0>
Qa synchronous FSM Output SSV
H17
LED<1>
Qb synchronous FSM Output SSV
K15
LED<2>
Qc synchronous FSM Output SSV
J13
LED<3>
Qd synchronous FSM Output SSV
N14
LED<4>
Not used in this assignment
R18
LED<5>
Z Output Logic (asynchronous)
V17
LED<6>
Not used in this assignment
U17
LED<7>
Clk_Q asynchronous FSM Output SSV
U16
The Digilent Nexys 4 DDR has sixteen switches and five push-buttons. These are connected to theArtix-7 integrated circuit in the following manner:
Original Digilent Net Name
Synchronous FSM Signal
Artix-7 I/O Pin Number
SW<0>
JAM_A synchronous input
J15
SW<1>
JAM_B synchronous input
L16
SW<2>
JAM_C synchronous input
M13
SW<3>
JAM_D synchronous input
R15
SW<4>
JAM_Enable synchronous input
R17
SW<5>
Not used in this assignment
T18
SW<6>
Not used in this assignment
U18
SW<7>
Not used in this assignment
R13
BTNC
Not used in this assignment
N17
BTNU
Clk_Set asynchronous input
M18
BTNL
Not used in this assignment
P17
BTNR
Not used in this assignment
M17
BTND
Clk_Reset asynchronous input
P18
You can edit your own names for any pins within a ‘*.xdc’ hardware constraints file included within your project. All other pins should be commented out using a ‘#’ at the start of the line.
Finite State Machine Design – Programmable Logic Implementation. Page – 4
3.3 Assignment Specification – Stage 2, Implementation of a digital lock
The system diagram for the asynchronous electronic lock is shown in Figure 3. A five-digit code will be entered on a simulated keypad. This keypad will be connected via ten active-high signals to an asynchronous finite state machine. When the correct sequence has been detected, the solenoid door bolt locking the door will be retracted by a signal, Z. The operator will be assumed to open the door and this operation will be detected by a switch, Dr (causing a return to the idling state). When the lock is first powered-up it will be forced into a safe idling state by the signal Reset. The asynchronous finite state machine will move through states encoded by three, or more, bits, Qa, Qb, Qc, etc.
Qa Qb Qc
Z
Door Open Switch
Solenoid Bolt
Figure 3. System Diagram Your unique code sequence will be emailed to you.
It will be assumed that ten keys of a key-pad, the Door Open and the power-up reset are simulated by twelve switches mounted on the Digilent Nexys4 DDR board.
Please use the following to ease the demonstration burden on staff.
The Digilent Nexys 4 DDR has sixteen LEDs. These are connected to the Artix-7 integrated circuit in the following manner:
1
2
3
4
5
6
k4 Asynchronous k5 Finite State
k6
k7
k8
k9 Reset Dr
7
8
9
0
Original Digilent Net Name
Asynchronous FSM Signal
Artix-7 I/O Pin Number
LED<0>
Qa asynchronous FSM Output SSV
H17
LED<1>
Qb asynchronous FSM Output SSV
K15
LED<2>
Qc asynchronous FSM Output SSV
J13
LED<3>
[Optionally used for Qd]
N14
LED<4>
[Optionally used for Qe]
R18
LED<5>
[Optionally used for Qf]
V17
LED<6>
Not used in this assignment
U17
LED<7>
Z Output Logic (asynchronous)
U16
Finite State Machine Design – Programmable Logic Implementation. Page – 5
k0 k1 k2 k3
Machine
The Digilent Nexys 4 DDR has sixteen switches and five push-buttons. These are connected to theArtix-7 integrated circuit in the following manner:
Original Digilent Net Name
Asynchronous FSM Signal
Artix-7 I/O Pin Number
SW<0>
Simulated keyboard key, rename to k0
J15
SW<1>
Simulated keyboard key, rename to k1
L16
SW<2>
Simulated keyboard key, rename to k2
M13
SW<3>
Simulated keyboard key, rename to k3
R15
SW<4>
Simulated keyboard key, rename to k4
R17
SW<5>
Simulated keyboard key, rename to k5
T18
SW<6>
Simulated keyboard key, rename to k6
U18
SW<7>
Simulated keyboard key, rename to k7
R13
SW<8>
Simulated keyboard key, rename to k8
T8
SW<9>
Simulated keyboard key, rename to k9
U8
SW<10>
Not used in this assignment
R16
SW<11>
Door open switch, rename to Dr
T13
SW<12>
Not used in this assignment
H6
SW<13>
Power-up reset, rename to Reset
U12
You can edit your own names for any pins within a ‘*.xdc’ hardware constraints file included within your project. All other pins should be commented out using a ‘#’ at the start of the line.
Design, construct, test, verify and write an effective field note book for a five-digit electronic lock. Your design should incorporate features to eliminate key bounce whilst still rejecting attempts by hostile users to unlock the door. As an asynchronous design, no flip-flops may be included; you may only use AND, OR and NOT gates. Particular care should be taken in the avoidance of race hazards.
3.4 Presentation of Deliverables
The presentation of the deliverables will consist of a simulation demonstration of the synchronous and asynchronous machines to the lecturer, simulation, validation (in the form that a lawyer can understand).
It is not unusual for the test bench to include many hundreds of lines of code to adequately cover the performance of the machines.
Remember
Credit will be given to those students who are able to communicate formal testing and verification methods in a precise and concise manner.
Do not forget to include into your log-book the source code, the (well-commented) simulation vectors and proof that the test vectors were accepted by the simulator.
Finite State Machine Design – Programmable Logic Implementation. Page – 6