FIT1047 – Week 2
hour 2 (Continued)
Introduction to computer systems, networks and security
Reference: https://www.alexandriarepository.org/syllabus/introduction-to-computer-systems-networks-and-security/
Reference: Linda Null, Julia Lobur. The essentials of computer organization and architecture. Fourth edition, 2015. Jones & Bartlett
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Converting to Sum of Products
We are interested in the values of the variables that make the function True (=1)
1. 2.
Using the Truth Table, make groups of ANDed results in a True function value
OR together each group of variables
Converting to Sum of Products: Example
variables (or negated variables), such that each group
F(x,y,z) xyz xyz xy z xyz
xyz
Reference: Linda Null, Julia Lobur. The essentials of computer organization and architecture. Fourth edition, 2015. Jones & Bartlett Learning.
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Converting to Product of Sums
We are interested in the values of the variables that make the function False (=0)
1. Complement all the function values (function output)
2. Using the Truth Table, make groups of ANDed variables (or negated variables), such that each group results in a True value for
the complement of the function (False value for the function)
3. OR together each group of variables This yields the complement of the function
4. Take the complement of this complement This yields the function itself
Converting to Product of Sums: Example
F(x, y, z) x y z x y z xyz (x y z)(x y z)(xyz)
(x y z)(x y z)(x y z) Reference: Linda Null, Julia Lobur. The essentials of computer organization and architecture. Fourth edition, 2015. Jones & Bartlett Learning.
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7 rules for working with Karnaugh-Maps (K-map)
Rule 1: No group can contain a zero.
Rule 2: Groups may be horizontal/vertical/square, but never diagonal.
Rule 3: Groups must contain 1,2,4,8,16,32 ……….(powers of 2) cells. Rule 4: Each group must be as large as possible.
Rule 5: Groups can overlap.
Rule 6: Each 1 must be part of at least one group.
Rule 7: Groups may wrap around the map.
Karnaugh-maps are useful for smaller Boolean functions. Automated algorithms for optimization are used for bigger functions.
Converting to Sum of Products: Example
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F(x,y,z) xyz xyz xy z xyz
xyz
Reference: Linda Null, Julia Lobur. The essentials of computer organization and architecture. Fourth edition, 2015. Jones & Bartlett Learning.
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FIT1047 TUTORIAL 2 (week-2)
METHOD – II : Using K-maps
1 1
1 1
=A𝐁+C
1
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FIT1047 TUTORIAL 2 (week-2)
METHOD – I : Using Boolean Identities
Reference: Linda Null, Julia Lobur. The essentials of computer organization and architecture. Fourth edition, 2015. Jones & Bartlett Learning.
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FIT1047 TUTORIAL 2 (week-2)
=A𝐁+C
Simulate using logisim
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Summarize topics of first 2 weeks
● A little bit of history
● Vacuum tubes and transistors
● bit, byte, word (8bit/16bit/32bit/64bit)
● Numbering systems (base 2, base 10, base 16)
● Conversion between numbering systems
● Signed integer representations (sign/magnitude, 1’s complement,
2’s complement)
● Properties of 2’s complement, adding 2’s complement numbers
● Floating point representation
● Properties of floating point, precision, rounding
● Characters: ASCII and Unicode
● Error detection: Parity bits, Checksum, CRC
● Boolean Logic AND, OR, NOT, XOR, NAND, NOR
● Logic gates
● Simple logic circuits
● Boolean Algebra, Laws
● Karnaugh Maps/K-maps
FIT1047 – Week 3 Central Processing Units, Part 1
Reference: https://www.alexandriarepository.org/syllabus/introduction-to-computer-systems-networks-and-security/
https://marie.js.org https://marie.js.org/book.pdf
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Recap
In Weeks 1 and 2 we have seen
● Number systems, binary
● Boolean logic
● Basic logic gates
Now let’s put them together to build a computer.
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Overview
● CPUs
● Machine code and assembly language
● Combinational circuits
○ Adders
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CPUs
A Central Processing Unit is the “brain” of a computer.
● Built out of logic gates
● Executes instructions
● Connected to memory and Input/Output devices (I/O)
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CPUs
A module from a IBM 700 series computer
with eight vacuum tubes
https://en.wikipedia.org/wiki/IBM_700/7000_series
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CPUs
Zilog Z80
(popular in some 1980s home computers)
https://en.wikipedia.org/wiki/Zilog_Z80
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CPUs
Intel Core i7
(top and bottom view)
Developer Manufacturer
Type
Introduction Architecture Microprocessor arch Word size
Intel
Intel
Microprocessors
May 30, 2017 (announced)
High-performance, high core count x86 desktop processors Skylake
64 bit
https://en.wikipedia.org/wiki/Intel_Core
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CPUs
ESP8266
Microcontroller with WiFi
($12.50)
Can be used to build “smart things” (IoT)
https://en.wikipedia.org/wiki/ESP8266
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High-level Programs
public class HelloWorld {
public static void main(String[] args) {
System.out.println(“Hello, World”);
}
}
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High-level Programs
import sys
name = sys.argv[1]
print ‘Hello, ‘ + name + ‘!’
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High-level Programs
int: n;
array[0..n-1] of var 0..n: s;
constraint forall(i in 0..n-1) (
s[i] = sum(j in 0..n-1)(s[j]=i)
);
solve satisfy;
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Programs
What do all these have in common?
● None of them can be executed directly by the CPU
● They are compiled or interpreted.
● CPUs can only execute machine
code.
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Monash University
Program Translation Process
Source code
Compiler Assembly code
Assembler
Object code
Runtime Library
Source code
Compiler Assembly code
Assembler Object code
Linker
Source code
Compiler Assembly code
Assembler
Object code
Executable code
High-level language
often done together
Machine language
(+ external references)
Loader
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What’s Machine Code
● A very simple computer language.
● Different for each CPU architecture
(https://ipfs.io/ipfs/QmXoypizjW3WknFiJnKLwHCnL72vedxjQkDDP1mXWo6uco/wiki/List_of_CPU_architectures.html )
○ e.g. different machine code in your smartphone, your laptop and your
washing machine
● Machine code programs are
○ Sequences of instructions
○ Stored in memory
○ Each instruction is encoded into one or more words
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Machine Code
The instructions that a particular type of CPU understands are called the Instruction Set Architecture (ISA)
What does a CPU need to be able to do?
● Do some maths (add, subtract, multiply, compare, …)
● Move data between memory, CPU and I/O
● Execute conditionals and loops
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Memory
Think of it as a sequence of “boxes”:
1004 3005 2006 7000 008E 0D80 0000
address0 1 2 3 4 5 6
Each box contains a value (here: a 16-bit number).
…
This could be a machine code instruction, or data.
We give each box an address: the number of the box, starting from 0.
Memory Hierarchy – Speed and Size
Reference: Linda Null, Julia Lobur. The essentials of computer organization and architecture. Fourth edition, 2015. Jones & Bartlett Learning.
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Registers
Very fast, very small memory inside the CPU
● Each register can store a single word (like one “box”)
● General purpose (GP) register:
○ Used by CPU to store temporary values for calculations
○ Can be used like a variable in programs
● CPU contains fixed small number (e.g. 16 GP registers for Intel CPUs)
● Special purpose register:
○ Used internally to enable CPU operations
○ Cannot be used directly in programs
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Assembly Language
Machine code is hard to write and read.
Example: what does 0010000000000110 mean? We use assembly language:
● Each instruction has a mnemonic, a word that is easy to remember
● Assembly language can be translated easily into machine code
○ Each line in the program is one instruction in machine code
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Assembly Instructions
These are not real instructions, just examples. ● Load 0xA003, R0
Load the number stored in memory at address A003 into GP register R0
● Add R0, R1, R2
Add the number stored in R0 to the number stored in R1, store the result in R2
● Store R0, 0xA004
Store the number in R0 into memory address A004
● Jump 0x1000
Continue program execution at address 1000
https://marie.js.org/book.pdf
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MARIE: A basic CPU simulator
Very basic machine architecture:
● MARIE (Machine Architecture that is Really Intuitive and Easy)
● Each memory location (“box”) holds a 16 bit word
● The CPU has only one GP register (called AC)
● Each instruction is a 16 bit word
○ Composed of an opcode (4 bits) and an address (12 bits=212 = 4096 address locations)
○ Example: 0001000110001110
Load
“Load from memory address 18E into AC register”
https://marie.js.org/book.pdf
18E in Hexadecimal
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MARIE instructions
Opcode
Assembly instruction
0001
Load
0010
Store
0011
Add
0100
Subt
0111
Halt
1000
Skipcond
1001
Jump
(we will see a few more instructions later)
https://marie.js.org/book.pdf
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MARIE programming
We use a simulator (see link on Moodle) https://marie.js.org/
Let’s write a small program that adds two numbers.
Pseudocode:
1. Load first number from memory into AC
2. Add second number from memory to AC
3. Store result from AC into memory
4. Stop
https://marie.js.org
12-Bits
16-Bits
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MARIE programming
Address(HEX)
Memory contents ( 16 bits)
Instruction
Data (decimal)
000
0001000000000100
Load 004
001
0011000000000101
Add 005
002
0010000000000110
Store 006
003
0111000000000000
Halt
004
0000000010001110
142
005
0000110110000000
3456
006
0000000000000000
0
Note: program and data share the same memory! https://marie.js.org/book.pdf
After Execution the address 006 = 0E0E in HEX = 3598 in DEC
https://marie.js.org/book.pdf
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Constructing a MARIE CPU
Circuits required to build a MARIE CPU:
● Perform simple maths (addition, subtraction, comparison)
● Store and load data in registers and memory
● Fetch, decode and execute instructions
Let’s start with the basics.
Combinational Circuits
(output is a function of the inputs)
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Adders
Let’s look at the most basic case: Adding two one-bit numbers.
Carry-out
Result
Input bit 1 Input bit 2
= Input bit 1 = Input bit 1
AND Input bit 2 XOR Input bit 2
Input bit 1
Input bit 2
0 + 0 = 00
0 + 1 = 01
1 + 0 = 01
1 + 1 = 10
Carry-out
Result
Result
Carry-out
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Full Adders
Adding three one-bit numbers.
Input bit 1
Input bit 2
Input bit 1
Input bit 2 Carry-in
0 + 0 + 0 = 00
0 + 0 + 1 = 01
0 + 1 + 0 = 01
0 + 1 + 1 = 10
1 + 0 + 0 = 01
1 + 0 + 1 = 10
1 + 1 + 0 = 10
1 + 1 + 1 = 11
Carry-out
Carry-out
Carry-in
Result
Result
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Ripple-Carry Adder
Add two 3-bit numbers (A+B=C):
A= 111 B= 001 1
———– C =1001
FIT1047 – Week 3 Central Processing Units, Part 2
Reference: https://www.alexandriarepository.org/syllabus/introduction-to-computer-systems-networks-and-security/
https://marie.js.org https://marie.js.org/book.pdf
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Overview
● Arithmetic / Logic Units (ALUs)
● Sequential circuits
○ Flip flops, registers, counters
○ memory ● Control
○ Executing a program
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Decoders
Activate one output based on a binary number.
A digital decoder transforms a set of digital input signals into an equivalent decimal code
at its output.
AB
http://www.cburch.com/logisim/
It is free! (Logisim is open-source (GPL).)
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Encoders
A simple encoder or simply an encoder in digital electronics is a one-hot to binary converter. That is, if there are 2n input lines, and at most only one of them will ever be high, the binary code of this ‘hot’ line is produced on the n-bit output lines.
http://www.cburch.com/logisim/
It is free! (Logisim is open-source (GPL).)
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Multiplexers
Select one of several inputs based on selector binary combination to output
http://www.cburch.com/logisim/
It is free! (Logisim is open-source (GPL).)
Arithmetic Logic Unit (ALU)
An ALU is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and GPUs.
A single CPU, FPU or GPU may contain multiple ALUs.
It is free! (Logisim is open-source (GPL).)
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ALU
Implements basic computations:
● Integer addition, subtraction (in more complex CPUs: multiplication)
● Comparisons
● Bitwise Boolean operations (AND, OR, NOT)
● Shifting
Inputs:
● Two n-bit operands
● Op-code (determines the operation to perform)
Outpus:
● n-bit result and status flags (overflow? error?)
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ALU
How does the circuit decide which operation to perform?
● Simply do all operation in parallel
● Then choose the result prescribed by the op-code Sounds like a job for a MULTIPLEXER (simply MUX)
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ALU
Select one of several inputs based on selector binary combination(opcode) to output
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Week-4 Online Test Second half of the Lecture
• The test is worth 15% of the unit marks
• The test is open book
• The test is for 60 Minutes
• All questions are MCQ
• In total 40 MCQ’s worth 60 Marks
• All the Best!
Sequential Circuits (output depends on sequence of inputs)
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Set/reset latch
Circuit in Reset state
Circuit is latched in Set state
𝐒
But digital circuits use a single bit for data!
𝐑
𝐐
http://www.cburch.com/logisim/
It is free! (Logisim is open-source (GPL).)
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D flip-flop
● Two inputs:
○ The bit to be stored
○ A signal: read or write mode
● One output:
○ The bit currently stored
D = input Data
> =clock = 1 write, 0 read
http://www.cburch.com/logisim/
It is free! (Logisim is open-source (GPL).)
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Registers
● Very fast memory inside the CPU
● Some special purpose registers
○ PC, IR, MBR, MAR (for MARIE)
● Some general purpose registers ○ AC (MARIE), AH/AL, BH/BL,
CH/CL, DH/DL (x86) ● Fixed bit width
○ E.g. 16 bit in MARIE
○ 16/32 or 64 bits in modern
processors
http://www.cburch.com/logisim/
It is free! (Logisim is open-source (GPL).)
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Register file
● Collection of registers
● Each implemented using n
flip-flops (for n bits)
● n inputs and outputs
● Additional input: which register
to write to
● Additional input: which register
to read from
http://www.cburch.com/logisim/
It is free! (Logisim is open-source (GPL).)
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Register file
http://www.cburch.com/logisim/
It is free! (Logisim is open-source (GPL).)
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MARIE architecture Register file
Address bus
Data bus
Memory
Control Unit
https://marie.js.org/book.pdf
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Control Unit
● Controls fetch-decode-execute cycle
● Switches control signals on and off:
○ Each signal is a “wire” inside the CPU
○ Which register to read/write
○ Which memory address to read/write
○ Which operation to perform in the ALU
● Needs to “know” which signals to switch on/off for each instruction Let’s specify, for each instruction, what to do!
https://marie.js.org/book.pdf
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Register Transfer Language (RTL)
● Break down instructions into small steps
● CPU performs one step per clock cycle
● Each step transfers data between registers and/or memory
https://marie.js.org/book.pdf
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RTL: fetch
1. MAR ← PC
2. MBR ← M[MAR]
3. IR ← MBR
4. PC ← PC+1
load PC into memory address register
load value from memory (M) into memory buffer register load value from MBR into instruction register
increment PC to point at next instruction
https://marie.js.org/book.pdf
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RTL: decode
5. MAR ← X load address X from IR into MAR
6. MBR ← M[MAR] load value from memory into MBR
Some instruction need both of these steps, some just step 5, some instructions need neither 5 nor 6.
https://marie.js.org/book.pdf
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RTL: execute
Depends on the concrete instruction (of course). Example: Add X
7. AC ← AC + MBR Example: Jump X 6. PC ← MAR
(place result of addition in AC)
(does not need decode step 6)
(load X, stored in MAR, into PC)
https://marie.js.org/book.pdf
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RTL: Full Add X instruction
1. MAR←PC
2. MBR ← M[MAR]
3. IR←MBR
4. PC ← PC+1
5. MAR←X
6. MBR ← M[MAR]
7. AC←AC+MBR
STEP 1. Fetch
The Control Unit sends a signal to the RAM in order to fetch the program and data, which is then stored in one of the CPU’s
register. To do so, the CPU makes use of a vital hardware path called the ‘address bus’ along which the program and data travels.
The Control Unit then increments the Program Counter (PC). The PC is an important register that keeps track of next program instruction due to be executed next.
STEP 2. Decode
The ‘instruction set’ of the CPU is designed to understand a specific set of commands, which serves to make sense of the instruction it has just fetched. This process is called ‘decode’.
STEP 3. Execute
This is the part of the cycle when data processing takes place, and the instruction is executed. Once the execute stage is complete, the CPU begins the cycle all over again.
https://marie.js.org/book.pdf
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Control Signals
Each RTL step tells us which control signals to switch on and off. Example: MBR ← M[MAR]
(load memory value from address stored in MAR into MBR)
● Switch register file to write into MBR
● Switch memory into read mode
https://marie.js.org/book.pdf
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Control Signals
Each RTL step tells us which control signals to switch on and off. Example: AC ← AC + MBR
(add value in MBR to value stored in AC, store result in AC)
● Switch register file to read from AC
● Switch register file to write into AC
● Switch ALU into “Add” mode (ALU always reads one operand from MBR)
https://marie.js.org/book.pdf
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MARIE architecture Register file
Address bus
Data bus
Memory
Control Unit
https://marie.js.org/book.pdf
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Outlook
Tutorials this week:
● MARIE programming
● Circuits for adding and subtracting
Next lecture:
● More MARIE instructions
● Memory
● Input/Output and Interrupts
FIT1047 – Week 4
Part 1:
Memory, Indirect Addressing
Reference: https://www.alexandriarepository.org/syllabus/introduction-to-computer-systems-networks-and-security/
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Recap
So far we saw
● Basic MARIE programming
● Combinational circuits (decoders, muxes, adders, ALUs)
● Sequential circuits (flip flops, registers)
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Overview
● Memory organisation ○ Addresses
● Accessing memory
○ Indirect addressing ○ Subroutines
Memory
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Memory
Think of it as a sequence of “boxes”:
1004 3005 2006 7000 008E 0D80 0000
0123456
Each box contains a value (here: a 16-bit number). This could be a machine code instruction, or data.
…
We give each box an address: the number of the box, starting from 0. Programs can read and change the value stored at a location.
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What is stored in memory?
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What is stored in memory?
The memory doesn’t know! The CPU doesn’t know! It’s up to the program to interpret the memory
in a certain way.
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Addressing
Most architectures store one byte per memory location: 10 05 AB 0F 8E 0D 00
0123456
So each byte has its own address. This is called byte-addressable.
…
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Addressing in MARIE
Some architectures (including MARIE) store one word per location:
…
1004 3005 2006 7000 008E 0D80 0000
0123456
So each word has its own address.
This is called word-addressable. Remember: In MARIE, one word is 16 bits.
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RAM
chip
row
Each chip = 214 =16384 bits
Column = 8 chips
Row = 8 chips
TotalRAMsize=64chipsX16384=26 X 214 =220 BITS=1Mbits
Each chip = 214 =16384 bits = 2KB TotalRAMsize=64chipsX2KB=128KB
A RAM module with 1 megabit (220 bit) capacity. Source: Wikipedia.
column
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RAM
Each module is made up of multiple chips Each chip has a fixed size L×W
● L: number of locations
● W: number of bits per location
E.g. 2K×8 means
= 2×210 locations of 8 bits each = 2×210×23 = 214 bits per chip
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RAM
64 chips, 214 bits each
Each chip = 214 =16384 bits
Column = 8 chips 220 BITS = 1Mbits
Row = 8 chips
Total RAM size = 64 chips X 16384 = 26 X 214 = 220 BITS = 1Mbits 2Byte=Word Addressable with 216 address with 16 bits
A RAM module with 1 megabit (220 bit) capacity. Source: Wikipedia.
How can we address individual locations?
1Byte= Byte Addressable with 217 address with 17 bits
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RTL of Basic MARIE Code
Register Transfer Language or RTL shows how the CPU (Assembler) works. Within the CPU there are many components including:
• AC or Accumulator : intermediate data is stored within the AC
• PC or Program Counter : as the name suggests it counts the current position of the code, each line has it’s own address
• MAR or Memory Access Register , stores or fetches the ‘data’ at the given address
• MBR or Memory Buffer Register , stores the data when being transferred
• IR or Instruction Register
Note that the end of each code, you will need to increment the PC by 1, so: PC ← PC + 1
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RTL of Basic MARIE Code
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RAM
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
211×8
8 rows
8 × 8 × 211 = 217 locations
Each address is 17 bits long!
8 columns = 8×211 bytes per row
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RAM addressing
Example address (17 bits):
010 110 00010010011
Row 2 Column 6 3-bit 3-bit
Byte addr 14710
We could implement this using MUXes!
● One MUX per chip selects the correct byte (here Byte address in dec: 147)
● One MUX per row selects the chip in a column (here: 6)
● One MUX per module selects the row (here: 2)
Indirect Addressing
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Accessing memory in MARIE
So far:
● Store X ● Load X ● Add X
● Jump X
Use value stored at X This is not very flexible!
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Indirect Addressing
Use address stored at X Comparison:
● Load X:
Load value stored at address X into AC.
● LoadI X:
Look up value stored at address X, use it as an address, load value from that address into AC.
(“indirect load”)
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Indirect Addressing
Example:
… 1004 3005 0206 7000 008E 0D80 0EA3 … 200 201 202 203 204 205 206
Load 202: Load value from address 202 into AC. Result: AC=0206.
LoadI 202: Look up value stored at address 202. Value is 0206. Then load value from that address into AC. Result: AC=0EA3.
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Indirect Addressing
Advantages:
● Addresses don’t need to be hard-coded into our program code
● We can compute the address!
● This enables important programming patterns, e.g. looping through a list of
values
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Indirect Addressing: Example
List of numbers
00C One, DEC1 00D Sum, DEC0 00E Addr, HEX 00F 00F DEC 70
010 DEC 73
011 DEC 84
012 DEC 0
000 Loop, 001
002
003
004
005
006
007
008
009 End,
00A
00B
LoadI Addr /AC=70,73,84,0 SkipCond 800 /AC≠0, stop if 0 Jump End AddSum/AC,AC←AC+sum=0 Store Sum /Sum = AC
Load Addr Add One Store Addr Jump Loop Load Sum Output Halt
Addr incr 00F to 010
Program computes sum of a list of numbers.
Note: length of list is not hard-coded!
End of list indicated byDEC 0
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Indirect Addressing
Other instructions that work with indirect addressing:
● AddI X:
Use address stored at X, load value from that address and add to value currently stored in AC.
● JumpI X:
Jump to address stored at address X.
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RTL for LoadI X
1. MAR←PC
2. MBR ← M[MAR]
3. IR←MBR
4. PC ← PC+1
5. MAR←X
6. MBR ← M[MAR]
7. MAR ← MBR
8. MBR ← M[MAR]
9. AC←MBR
fetch
decode execute
Subroutines
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Subroutines
AKA procedures, functions, methods.. A piece of code that
● Has a well-defined function
● Needs to be executed often
● We can call, passing arguments to it
● Returns to where it was called from
FIT1047 Monash University
Subroutines in Machine Code
ISAs provide support for subroutines. In MARIE:
● JnS X:
Stores PC into X, then jumps to X+1. X hold the return address.
(“Jump and Store”)
● JumpI X:
Jump to address stored at X. Returns to the calling code.
FIT1047 Monash University
Subroutine Example
Load FortyTwo /AC holds 42
Store Print_Arg / Stores Contents of AC into Address Print_Arg (DEC 0) JnS Print / Jumps and Store: Stores value of PC at address Print=0 then
/ increments PC to Print+1 = 1 Halt /End the program
FortyTwo, DEC 42
/ Subroutine that prints one number
Print_Arg, DEC 0 Print, HEX 0
Load Print_Arg Output
JumpI Print
/ put argument here
/ holds return address
/ return to caller
FIT1047 Monash University
Subroutine Example
/Subroutine to double: subroutine_double.mas
loop, Input Store Val
Output
Store Temp Jns ACDouble
Load Temp
Output
Jump loop
Val, Dec 00
/ ***** Subroutine *****
/ get value
ACDouble,
Temp, Dec 0
Dec 0
Load Temp
Add Temp
Store Temp JumpI ACDouble
/ return address placed here / Loading Temp
/ Doubling AC
/ Save Temp
/ / / /
/ /
store value as argument temp
call subroutine ACDouble.
Jns=Jumps and Stores: Stores PC at addr ACDouble and jumps to ACDouble+1 load subroutine temporary data
Infinite loop
Initial Value
/ return with value in AC / Empty: subroutine argument
FIT1047 Monash University
Summary + Outlook
Memory:
● Stores bits, up to the program to interpret them
● Need one address per byte (in byte-addressable memory) or word (in word-
addressable memory, e.g. MARIE) Indirect addressing + subroutines:
● Important if we want to write more complex programs Labs this week:
● More MARIE programming
FIT1047 Monash University
Week-4 Online Test second half of the Lecture 22nd March 2021(3-4 PM)
• The test is worth 15% of the unit marks
• Under Week-4 section in Moodle (Password protected)
• The test is close book
• The test is for 60 Minutes
• All questions are MCQ
• In total 40 MCQ’s worth 60 Marks
• All the Best!