Chapter 2
Assembly Language for x86 Processors 6th Edition
Chapter 2: x86 Processor Architecture
(c) Pearson Education, 2010. All rights reserved. You may modify and copy this slide show for your personal use, or for use in the classroom, as long as this copyright statement, the author’s name, and the title are not changed.
Kip Irvine
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Chapter Overview
General Concepts
IA-32 Processor Architecture
IA-32 Memory Management
Components of an IA-32 Microcomputer
Input-Output System
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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General Concepts
Basic microcomputer design
Instruction execution cycle
Reading from memory
How programs run
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Basic Microcomputer Design
clock synchronizes CPU operations
control unit (CU) coordinates sequence of execution steps
ALU performs arithmetic and bitwise processing
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Clock
synchronizes all CPU and BUS operations
machine (clock) cycle measures time of a single operation
clock is used to trigger events
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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What’s Next
General Concepts
IA-32 Processor Architecture
IA-32 Memory Management
Components of an IA-32 Microcomputer
Input-Output System
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Cache Memory
High-speed expensive static RAM both inside and outside the CPU.
Level-1 cache: inside the CPU
Level-2 cache: outside the CPU
Cache hit: when data to be read is already in cache memory
Cache miss: when data to be read is not in cache memory.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Buses
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Instruction Execution Cycle
Fetch
Decode
Fetch operands
Execute
Store output
Instruction Execution Cycle
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Reading from Memory
Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are:
address placed on address bus
Read Line (RD) set low
CPU waits one cycle for memory to respond
Read Line (RD) goes to 1, indicating that the data is on the data bus
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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How a Program Runs
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Multitasking
OS can run multiple programs at the same time.
Multiple threads of execution within the same program.
Scheduler utility assigns a given amount of CPU time to each running program.
Rapid switching of tasks
gives illusion that all programs are running at once
the processor must support task switching.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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IA-32 Processor Architecture
Modes of operation
Basic execution environment
Floating-point unit
Intel Microprocessor history
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Modes of Operation
Protected mode
native mode (Windows, Linux)
Real-address mode
native MS-DOS
System management mode
power management, system security, diagnostics
Virtual-8086 mode
hybrid of Protected
each program has its own 8086 computer
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Basic Execution Environment
Addressable memory
General-purpose registers
Index and base registers
Specialized register uses
Status flags
Floating-point, MMX, XMM registers
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Addressable Memory
Protected mode
4 GB
32-bit address
Real-address and Virtual-8086 modes
1 MB space
20-bit address
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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General-Purpose Registers
Named storage locations inside the CPU, optimized for speed.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
271.unknown
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Accessing Parts of Registers
Use 8-bit name, 16-bit name, or 32-bit name
Applies to EAX, EBX, ECX, and EDX
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Index and Base Registers
Some registers have only a 16-bit name for their lower half:
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Some Specialized Register Uses (1 of 2)
General-Purpose
EAX – accumulator
ECX – loop counter
ESP – stack pointer
ESI, EDI – index registers
EBP – extended frame pointer (stack)
Segment
CS – code segment
DS – data segment
SS – stack segment
ES, FS, GS – additional segments
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Some Specialized Register Uses (2 of 2)
EIP – instruction pointer
EFLAGS
status and control flags
each flag is a single binary bit
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Status Flags
Carry
unsigned arithmetic out of range
Overflow
signed arithmetic out of range
Sign
result is negative
Zero
result is zero
Auxiliary Carry
carry from bit 3 to bit 4
Parity
sum of 1 bits is an even number
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Intel Microprocessor History
Intel 8086, 80286
IA-32 processor family
P6 processor family
CISC and RISC
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Early Intel Microprocessors
Intel 8080
64K addressable RAM
8-bit registers
CP/M operating system
S-100 BUS architecture
8-inch floppy disks!
Intel 8086/8088
IBM-PC Used 8088
1 MB addressable RAM
16-bit registers
16-bit data bus (8-bit for 8088)
separate floating-point unit (8087)
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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The IBM-AT
Intel 80286
16 MB addressable RAM
Protected memory
several times faster than 8086
introduced IDE bus architecture
80287 floating point unit
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Intel IA-32 Family
Intel386
4 GB addressable RAM, 32-bit registers, paging (virtual memory)
Intel486
instruction pipelining
Pentium
superscalar, 32-bit address bus, 64-bit internal data path
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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64-bit Processors
Intel64
64-bit linear address space
Intel: Pentium Extreme, Xeon, Celeron D, Pentium D, Core 2, and Core i7
IA-32e Mode
Compatibility mode for legacy 16- and 32-bit applications
64-bit Mode uses 64-bit addresses and operands
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Intel Technologies
HyperThreading technology
two tasks execute on a single processor at the same time
Dual Core processing
multiple processor cores in the same IC package
each processor has its own resources and communication path with the bus
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Intel Processor Families
Currently Used:
Pentium & Celeron – dual core
Core 2 Duo – 2 processor cores
Core 2 Quad – 4 processor cores
Core i7 – 4 processor cores
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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CISC and RISC
CISC – complex instruction set
large instruction set
high-level operations
requires microcode interpreter
examples: Intel 80×86 family
RISC – reduced instruction set
simple, atomic instructions
small instruction set
directly executed by hardware
examples:
ARM (Advanced RISC Machines)
DEC Alpha (now Compaq)
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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What’s Next
General Concepts
IA-32 Processor Architecture
IA-32 Memory Management
Components of an IA-32 Microcomputer
Input-Output System
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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IA-32 Memory Management
Real-address mode
Calculating linear addresses
Protected mode
Multi-segment model
Paging
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Real-Address mode
1 MB RAM maximum addressable
Application programs can access any area of memory
Single tasking
Supported by MS-DOS operating system
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Segmented Memory
Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
linear addresses
one segment
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
273.unknown
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Calculating Linear Addresses
Given a segment address, multiply it by 16 (add a hexadecimal zero), and add it to the offset
Example: convert 08F1:0100 to a linear address
Adjusted Segment value: 0 8 F 1 0
Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Your turn . . .
What linear address corresponds to the segment/offset address 028F:0030?
028F0 + 0030 = 02920
Always use hexadecimal notation for addresses.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Your turn . . .
What segment addresses correspond to the linear address 28F30h?
Many different segment-offset addresses can produce the linear address 28F30h. For example:
28F0:0030, 28F3:0000, 28B0:0430, . . .
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Protected Mode (1 of 2)
4 GB addressable RAM
(00000000 to FFFFFFFFh)
Each program assigned a memory partition which is protected from other programs
Designed for multitasking
Supported by Linux & MS-Windows
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Protected mode (2 of 2)
Segment descriptor tables
Program structure
code, data, and stack areas
CS, DS, SS segment descriptors
global descriptor table (GDT)
MASM Programs use the Microsoft flat memory model
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Flat Segment Model
Single global descriptor table (GDT).
All segments mapped to entire 32-bit address space
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
274.unknown
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Multi-Segment Model
Each program has a local descriptor table (LDT)
holds descriptor for each segment used by the program
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
275.unknown
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Components of an IA-32 Microcomputer
Motherboard
Video output
Memory
Input-output ports
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Motherboard
CPU socket
External cache memory slots
Main memory slots
BIOS chips
Sound synthesizer chip (optional)
Video controller chip (optional)
IDE, parallel, serial, USB, video, keyboard, joystick, network, and mouse connectors
PCI bus connectors (expansion cards)
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Intel D850MD Motherboard
dynamic RAM
Pentium 4 socket
Speaker
IDE drive connectors
mouse, keyboard, parallel, serial, and USB connectors
AGP slot
Battery
Video
Power connector
memory controller hub
Diskette connector
PCI slots
I/O Controller
Firmware hub
Audio chip
Source: Intel® Desktop Board D850MD/D850MV Technical Product Specification
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Intel 965 Express Chipset
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Video Output
Video controller
on motherboard, or on expansion card
AGP (accelerated graphics port technology)*
Video memory (VRAM)
Video CRT Display
uses raster scanning
horizontal retrace
vertical retrace
Direct digital LCD monitors
no raster scanning required
* This link may change over time.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Sample Video Controller (ATI Corp.)
128-bit 3D graphics performance powered by RAGE™ 128 PRO
3D graphics performance
Intelligent TV-Tuner with Digital VCR
TV-ON-DEMAND™
Interactive Program Guide
Still image and MPEG-2 motion video capture
Video editing
Hardware DVD video playback
Video output to TV or VCR
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Memory
ROM
read-only memory
EPROM
erasable programmable read-only memory
Dynamic RAM (DRAM)
inexpensive; must be refreshed constantly
Static RAM (SRAM)
expensive; used for cache memory; no refresh required
Video RAM (VRAM)
dual ported; optimized for constant video refresh
CMOS RAM
complimentary metal-oxide semiconductor
system setup information
See: Intel platform memory (Intel technology brief: link address may change)
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Input-Output Ports
USB (universal serial bus)
intelligent high-speed connection to devices
up to 12 megabits/second
USB hub connects multiple devices
enumeration: computer queries devices
supports hot connections
Parallel
short cable, high speed
common for printers
bidirectional, parallel data transfer
Intel 8255 controller chip
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Input-Output Ports (cont)
Serial
RS-232 serial port
one bit at a time
uses long cables and modems
16550 UART (universal asynchronous receiver transmitter)
programmable in assembly language
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Device Interfaces
ATA host adapters
intelligent drive electronics (hard drive, CDROM)
SATA (Serial ATA)
inexpensive, fast, bidirectional
FireWire
high speed (800 MB/sec), many devices at once
Bluetooth
small amounts of data, short distances, low power usage
Wi-Fi (wireless Ethernet)
IEEE 802.11 standard, faster than Bluetooth
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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What’s Next
General Concepts
IA-32 Processor Architecture
IA-32 Memory Management
Components of an IA-32 Microcomputer
Input-Output System
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Levels of Input-Output
Level 3: High-level language function
examples: C++, Java
portable, convenient, not always the fastest
Level 2: Operating system
Application Programming Interface (API)
extended capabilities, lots of details to master
Level 1: BIOS
drivers that communicate directly with devices
OS security may prevent application-level code from working at this level
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Displaying a String of Characters
When a HLL program displays a string of characters, the following steps take place:
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
282.unknown
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Programming levels
Assembly language programs can perform input-output at each of the following levels:
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
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Summary
Central Processing Unit (CPU)
Arithmetic Logic Unit (ALU)
Instruction execution cycle
Multitasking
Floating Point Unit (FPU)
Complex Instruction Set
Real mode and Protected mode
Motherboard components
Memory types
Input/Output and access levels
Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.
Central Processor Unit
(CPU)
Memory Storage
Unit
registers
ALU
clock
I/O
Device
#1
I/O
Device
#2
data bus
control bus
address bus
CU
one cycle
1
0
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Data
Address
CLK
ADDR
RD
DATA
Operating
system
User
Current
directory
System
path
Directory
entry
sends program
name to
gets starting
cluster from
searches for
program in
loads and
starts
Program
returns to
CS
SS
DS
ES
EIP
EFLAGS
16-bit Segment Registers
EAX
EBX
ECX
EDX
32-bit General-Purpose Registers
FS
GS
EBP
ESP
ESI
EDI
AH
AL
16 bits
8
AX
EAX
8
32 bits
8 bits + 8 bits
00000
10000
20000
30000
40000
50000
60000
70000
80000
90000
A0000
B0000
C0000
D0000
E0000
F0000
8000:0000
8000:FFFF
seg
ofs
8000:0250
0250
00000000
FFFFFFFF
(4GB)
physical RAM
00000000
Segment descriptor, in the
Global Descriptor Table
00040
– – – –
base address
limit
access
00040000
not used
3000
RAM
00003000
Local Descriptor Table
0002
00008000
000A
00026000
0010
base
limit
access
8000
26000
Application Program
OS Function
BIOS Function
Hardware
Level 0
Level 1
Level 2
Level 3