A few considerations….
■ Please do not abuse the CHAT feature on Zoom
■ Do not post irrelevant content on Zoom chat. This includes lab discussions during lecture time. You already have Discord for that!
■ Zoom saves a log of chat history along with user name. So I know who posts irrelevant stuff
■ If you post irrelevant stuff, actual questions posed by students get lost in the sea of chats!
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Operate: I-Type Instructions
■
◆ Example (using decimal notation): ★ ADDI $t1, $t2, 23
★ $t1 = $t2 + 23
Arithmetic Immediate Signed
◆ Can use hex notation (useful for masking): ★ ANDI $t1, $t2, 0x000F
★ $t1 = $t2 & 0x000F
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Logical Operations
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Regarding SUB instructions
★ SUB $t1, $t2, $t3
– Means ($t1) = ($t2) – ($t3)
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MIPS Overview – Commands
MIPS instructions can be broken down into 3 categories:
■
Data Movement
Move data between memory and registers
◆
★ For example: lw is load word, sw is store word ■ Operate
◆ Manipulate data directly
★ For example: add is addition, xor is logical
■ Control
◆ Change the sequence of instruction execution
★ For example: b is branch, jal is jump and link, ret is return
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Data-Movement: Load Instructions
■ Move data from memory to a register Data transfer
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Register
Memory
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“Endian”-ness of Memory adressing
■ MIPS is byte-addressable
■ Little Endian byte ordering
◆ Compare to Big Endian… (e.g. AVR or ARM) CSE 12 W 2021 7
Endianness
Big Endian: Most significant byte occupying lower address position Little Endian: Least significant byte occupying lower address position
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Endianness: Memory aid for exams
Least significant byte of data occupies lower address position in memory!
Little Endians
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Lol
Most significant byte of data occupies lower address position in memory!
Big Endians
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Indirect addressing
■ lw $t1, ($t2)
◆ $t2 contains a 32-bit address ◆ Effective address is $t2
◆ ($t1) = memory[$t2]
■ NOTE: lw $t1, $t2 is not valid syntax! Example:
Assume four 32-bit registers, Little Endian ordering in memory Reg0
Memory address
Reg1 1210 Reg2
Reg3
15 0x29 16
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lw Reg1, (Reg2); (Reg1)=?
(Reg1)= 0x FD 54 A5 99
0xA5 17
0x10 0xA0 0x09 0x00 0x99 0xA5 0x54 0xFD
8
9 10
11
12
13 14
0x01 0xFF
18 19
Base + offset addressing
■ lw $t1, 4($t2)
◆ $t2 contains a 32-bit address
◆ Instruction contains 16-bit immediate offset (4) ◆ Effective address is $t2+4
◆ $t1=memory[$t2+4]
■ NOTE: lw $t1, 0($t2) is the same as indirect addressing!
■ Immediate offset is 16-bit *signed* and we can load
adjacent words: ◆ lw $t1, -4($t2) ◆ lw $t2, 0($t2) ◆ lw $t3, 4($t2)
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Indirect addressing
Endian ordering in memory
Memory
address
8
9 10
11
12
13 14
15 16
17 18
19
0x10
0xA0
0x09
0x00
0x99
0xA5
0x54
0xFD
0x29
0xA5
0x01
0xFF
1210
Problem 1:
lw Reg1, 0(Reg2);
(Reg1)=?
(Reg1)= 0x FD 54 A5 99
Problem 2:
lw Reg1, 4(Reg2);
(Reg1)=?
(Reg1)= 0x FF 01 A5 29
Problem 3:
lw Reg1, -4(Reg2);
(Reg1)=?
(Reg1)= 0x 00 09 A0 10
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Example:
Assume four 32-bit registers, Little
Reg0
Reg1 Reg2
Reg3
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Load data sizes
■ Words are 32-bit values
◆ Load word (lw)
◆ Same size as the registers ◆ Same size as the addresses
■ Half-Words
◆ Load half word (lh)
◆ Are 16-bit values
◆ Same size as the immediate values
■ Bytes
◆ Load byte (lb) ◆ Are 8-bit values
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Data sizes (cont’d)
■ Where are half word and bytes placed?
◆ Half word is put in lower register bits [15:0] ◆ Byte is put in lower register byte [7:0]
■ What about the other bits?
◆ Half word
★ LH fills upper bits [31:16] with sign ★ LHU fillers upper bits [31:16] with 0
◆ Byte
★ LB fills upper bits [31:8] with sign ★ LBU fillers upper bits [31:8] with 0
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Data-Movement: Store Instructions
■ Move data from memory to a register Register to Memory
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Data transfer
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Memory
Register
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Data-Movement: Stores
■ Stores are similar to loads…
◆ Address modes are the same. ◆ Data sizes are the same.
★ Upper bits are ignored for byte and half word writes
◆ Except… register contents are put in memory. ★ sw $t1, 4($t2)
★ Memory[$t2+4] = ($t1)
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Indirect addressing
■ sw $t1, ($t2)
◆ $t2 contains a 32-bit address ◆ Effective address is $t2
◆ memory[$t2] = ($t1)
■ NOTE: sw $t1, $t2 is not valid syntax! Example:
Memory
address
8
9 10
11
12
13 14
15 16
17 18
19
Assume four 32-bit registers, Little Endian ordering in memory Reg0
BE BA FE CA
0xCAFEBABE Reg1 1210 Reg2
Reg3
sw Reg1, (Reg2); Mem[Reg2]=?
Mem[Reg2]= 0x CA FE BA BE
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Summary of Loads/Stores
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Use the GREEN!
Don’t use Grey!
MIPS Overview – Commands
MIPS instructions can be broken down into 3 categories:
■ Data Movement
◆ Move data between memory and registers
★ For example: lw is load word, sw is store word
■ Operate
◆ Manipulate data directly
★ For example: add is addition, xor is logical ■ Control
★
◆
Change the sequence of instruction execution
For example: b is branch, jal is jump and link, ret
is return
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Program Flow
■ Branches change the flow of instructions
◆ Default is to execute the next instruction
◆ If the condition is met it will execute the instruction at a label
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Conditional Branch (1)
■ Compares two registers ◆ Branch Equal (BEQ)
◆ Branch Not Equal (BNE)
■ Example:
◆ BEQ $t0, $t1, label
★ If $t0 == $t1, execute instruction at label next ★ Otherwise, execute instruction after BEQ
■ Often used to “skip over” some instructions
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Branch Example
Only 2 command executed:
beq
addi $t3, $0, 3
Notice blah_label get translated to 0x2….
Time for a class poll…
■ ■ ■
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Conditional Branch (2)
■ Considers only a single register for comparison and compares implicitly with zero
◆ Branch Greater than or Equal to Zero (BGEZ) ◆ Branch Greater than Zero (BGTZ)
◆ Branch Less than or Equal to Zero (BLEZ)
◆ Branch Less than Zero (BLTZ)
■ Example:
◆ BGTZ $t0, label
◆ If $t0>0, execute instruction at label next ◆ Otherwise, execute instruction after BGTZ
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