2
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/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a1_gpo|Src|computer.sch/CPU – simple_cpu_v1a/XLXI_14 – buf8
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/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a1_gpo|Src|computer.sch/CPU – simple_cpu_v1a/XLXI_8 – control_logic
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a1_gpo|Src|computer.sch/MEMORY – ram_256x16 – ram_256x16_arch
/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a1_gpo|Src|computer.sch/OUTPUT – reg_8
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/computer |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a1|Src|computer.sch/XLXI_14 – simple_cpu_v1a1
/computer |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a_gpo|Src|computer.sch/CPU – simple_cpu_v1a
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/computer |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|Src|computer.sch/CPU – simple_cpu_v1a/XLXI_1 – counter_8/XLXI_1 – reg_8
/computer |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|Src|computer.sch/CPU – simple_cpu_v1a/XLXI_1 – counter_8/XLXI_2 – add_8
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/computer |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1d_gpo|Src|computer.sch/CPU – simple_cpu_v1a
/computer |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1d_gpo|Src|computer.sch/MEMORY – ram_256x16 – ram_256x16_arch
/computer |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1d_gpo|Src|computer.sch/OUTPUT – reg_8
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/reg_8 |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|Src|reg_8.sch
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/simple_cpu_v1a |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|simple_cpu_v1a.sch/XLXI_2 – reg_8
/simple_cpu_v1a |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|simple_cpu_v1a.sch/XLXI_3 – reg_16
/simple_cpu_v1a |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|simple_cpu_v1a.sch/XLXI_4 – alu
/simple_cpu_v1a |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|simple_cpu_v1a.sch/XLXI_4 – mux_2_8
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/simple_cpu_v1a |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|simple_cpu_v1a.sch/XLXI_6 – mux_2_8
/simple_cpu_v1a |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|simple_cpu_v1a.sch/XLXI_7 – buf8
/simple_cpu_v1a |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a|simple_cpu_v1a.sch/XLXI_8 – control_logic
/simple_cpu_v1a1 |home|mike|Documents|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a1_gpo|Src|simple_cpu_v1a1.sch
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/testbench – behavior |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1a_gpo|computer_tb.vhd/uut – computer/OUTPUT – reg_8
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/testbench – behavior |mnt|hdd|Documents|Web|SimpleCpuDesign|simple_cpu_v1a_fpga|VHDL|simple_cpu_v1d_gpo|computer_tb.vhd/uut – computer/CPU – simple_cpu_v1a/XLXI_3 – reg_16
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