sch2sym -intstyle ise -family zynq -w -refsym reg_12 /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/Src/reg_12.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/reg_12.sym
sch2hdl -sympath /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/ipcore_dir -intstyle ise -family zynq -flat -suppress -vhdl reg_12_drc.vhf -w /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/Src/reg_12.sch