sch2sym -intstyle ise -family zynq -w -refsym register_file /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/register_file.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/register_file.sym
sch2sym -intstyle ise -family zynq -w -refsym register_file /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/register_file.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/register_file.sym
sch2sym -intstyle ise -family zynq -w -refsym register_file /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/register_file.sch /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/simple_cpu_v1d/register_file.sym
sch2hdl -sympath /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/ipcore_dir -intstyle ise -family zynq -flat -suppress -vhdl register_file_drc.vhf -w /home/mike/Documents/SimpleCpuDesign/simple_cpu_v1d_fpga/VHDL/register_file.sch