— TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY computer_tb IS
END computer_tb;
ARCHITECTURE behavior OF computer_tb IS
— Component Declaration
COMPONENT computer
PORT(
CLK : in std_logic;
CLR : in std_logic;
GPO : out std_logic_vector (7 downto 0) );
END COMPONENT;
COMPONENT debug
PORT (
CLK : IN STD_LOGIC ;
CLR : IN STD_LOGIC ;
ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0) );
END COMPONENT;
SIGNAL clk : std_logic;
SIGNAL clr : std_logic;
SIGNAL gpo : std_logic_vector (7 downto 0);
BEGIN
— Component Instantiation
uut: computer PORT MAP(
CLK => clk,
CLR => clr,
GPO => gpo);
clock : PROCESS
BEGIN
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
END PROCESS clock;
reset : PROCESS
BEGIN
clr <= '1';
wait for 200 ns;
clr <= '0';
wait;
END PROCESS reset;
END;