Computer Architecture
ARM Processor and Instruction Set
ARM Processor (features)
• ARM stands for Advanced RISC Machine and is the name associated with the leading developer of RISC based processors.
• First design in 1975 was 6502
•4000 transistors
•2 Mhz, 8 bits bus
•Took 26 cycles to add two integers •Implemented in the BBC computer
• In 1985 ARM1 •25000 transistors,
•8 MHz, 32 bit bus
•2 cycles to add two integers
•Implemented on Acorn Risc Machine
Example code
ldr r0,[addressA] ldr r1,[addressB] add r2,r0,r1
str r2,[addressC]
ARM Instruction Set
Unlike Intel, ARM does not manufacture chips, it just licenses the designs for other to optimize and manufacture.
What does this mean for the Instruction Set, it means that, there will be a consistency across all manufacturers in the language used to program these devices. This is because the manufacturers don’t have to compete with each other on the core processor features, but instead can focus on the features supporting it.
Registers for AArch64
• Armv8-A supports A32,T32 and A64 (AArch64)
• Most A64 instructions operate on registers. It is fixed-length 32-bit
instruction set.
• The architecture provides 31 general purpose registers. 64-bit X register
(X0..X30), or 32-bit W register (W0..W30).
• SP Stack pointer
• X30 is the LR link register. Contains return address
• PC Program counter. Memory address of currently execution instruction
• 32 registers for floating points.
• E.g. 32-bit integer addition: ADD W0, W1, W2 in this case the top 32 bits of the 64-bit register are zeroed
• E.g.64-bitintegeraddition:ADDX0,X1,X2
• https://developer.arm.com/documentation/den0024/a/ARMv8-Registers
ARM Instructions
The ARM processor also comes with it own set of assembly instructions. Below is a list
of a few of them that will be discussed throughout the rest of this module:
1. mov – copies values from one operand to another
2. add, adc, adds – adds operands
3. sub, subs– subtracts operands
4. and – performs bitwise AND of operands
5. orr – performs bitwise OR of operands
6. eor – performs bitwise XOR of operands
7. bl – performs a branch and link
8. bic – performs bitwise bit clearing of operands
9. cmp, tst – compare operands and sets bits in
10. b,bxx–conditionalandunconditionalloops
11. push,pop
12. ldr,str
https://developer.arm.com/documentation/dui0068/b/arm-instruction-reference
MOV data between operands
As mentioned previously the mov instruction is used to transfer data between operands. In most cases ARM only allows operation within the registers, the exception is for load and store operations which can move immediate data and data from memory. “mov” can have immediate values as an operand.
The instructions format of most ARM instructions will follow the form:
opcode
Common abbreviation of the instruction is as follows: mov Rd, Rn, Rm.
Rn can be any of the registers (R0-R15) and Rm(Op2) can be a register or an immediate value. The immediate value is within the range of 0-255 maximum. The second operand Rm can be shifted. The registers can hold 32 bit values.
Examples:
mov r0, r5
mov r1, #37
mov r1, #0x55
Addition
As stated before the format of most ARM instructions will follow the form: opcode dest, src1, src2
The add instruction is used to place the summation of the source operands into the destination operand.
The adc instruction is a variant of the add instruction and simply adds the carry flag value to the final value placed into the destination operand.
IMPORTANT:To update the CPSR register after an addition operation use ADDS These instructions allow for the addition of an immediate value.
Common abbreviation of the instruction add is as follows: add Rd, Rn, Op2
Op2 can be a register or immediate value.
Examples: lsl – logical shift left and alternatively (Logical shift Right – lsr)
add r1, r1, r5
add r1, r5 (same as above)
add r1, r1, r5, lsl #3
adc r1, r2, r3 (r1 = r2 + r3 + carry)
add r2, r1, #37
add r1, r2, #0x55
add r1, r1, r5, lsl #2
adc r1, r2, #3 (r1 = r2 + 3 +carry)
Subtraction
The sub instruction is used to place the subtraction of the source operands into the destination operand.
Common abbreviation of the instruction add is as follows: sub Rd, Rn, Op2
Op2 can be a register or immediate value. IMPORTANT:To update the CPSR register after a SUB use SUBS Examples:
sub r1, r1, r5
sub r2, r1, #37
sub r1, r1, r5, lsl #2
sub r1, r1, r5, lsl #0x2
sub r1, r5 (same as above)
sub r1, r2, #0x55
AND
The and instruction is used to place the bitwise result of and’ing the source operands, into the destination operand.
These instruction allow for the addition of an immediate value.
Common abbreviation of the instruction add is as follows: sub Rd, Rn, Op2
Op2 can be a register or immediate value. Examples:
1. and – performs bitwise AND of operands
and r1, r1, r5
and r2, r1, #37
and r1, r5 (same as above)
and r1, r2, #0x55
ORR and EOR
The ORR and XOR instruction is used to place the bitwise result of the OR, XOR’ing the source operands, into the destination operand.
These instruction allow for the manipulation with an immediate value. Common abbreviation of the instruction add is as follows: orr Rd, Rn, Op2
Op2 can be a register or immediate value. Examples:
orr r1, r1, r5
orr r2, r1, #37
eor r1, r5, r2
eor r1, r2, #0x55
Branch Instructions
The BL instruction represent the Branch and Link. It transfers execution to the code being referenced by the operand and saves the return address to the Link register. This is in contrast to the Intel processor which saves the return address to the stack.
This is an unconditional branch and will be immediately executed. It has a similar behavior to the CALL instruction in Intel. An odd feature of the ARM processor though is that the value stored in the Link Register is the address of the instruction after the return address. To perform a return operation the BX instruction is used which perform a Branch Exchange. This places the address in the LR into the PC register.
Example: next: bl fun1
adds r0, r0, r2 cmp r0, #0x10 bne next
fun1: bx lr
Branch Instructions – Conditional
Like the Intel JCC instructions the conditional branch instructions are affected by the status register. In the ARM processor the CPSR holds the flags being used to decide whether a BRANCH will be taken.
The instructions have the form: BXX where XX represents the conditions. Some examples include BCS, BEQ, BNE, BLS and BHI
Example of usage:
next:
adds r0, r0, r2 cmp r0, #0x10 bne next
Bit Clear and Testing Instructions
The BIC (Bit Clear) instruction used to clear, (make a bit zero), 1 or multiple bits.
•It does so by performing AND of operand 1 with the Negation of operand 2.
•For example: BIC R0, R1, #0x3;
•If the value in R1 was 0xFF the result of the following operation would be stored in R0.
R1
0000 0000 1111 1111
0xFFFC
1111 1111 1111 1100 – (this is the negated value of 0x3)
R0
0000 00001111 1100 (R0 would contain 0xFC)
Compare and Test behave exactly like their intel twins.
•CMP takes the values of the operands, simulates a subtraction operation and updates the CPSR flags based on the result without modifying the registers involved.
•TST takes the values of the operands, simulates a bitwise AND operation and updates the CPSR flags based on the result without modifying the registers involved.