CS计算机代考程序代写 cache arm assembly assembler 2021/8/23 CS 315 – Fall 2021 – Project06

2021/8/23 CS 315 – Fall 2021 – Project06
Project06 – Processor Implementation
Due
1. Thu May 13th at 8 AM to the Github Classroom repo published in Piazza
2. Submit all of the .dig files and .hex files required to run your simulation
3. Submit a link or PDF for your Control Unit spreadsheet
4. Project06 will be graded in an Interactive Grading meeting. Please sign up using the spreadsheet published in your section’s Piazza
Requirements
1. You will implement and simulate a simplified ARM microarchitecture in Digital
1. You may use any of Digital’s library of components
2. We will introduce some new and useful tools and techniques for Digital in lecture
2. Your processor must be able to execute the following programs: fib_rec_s, find_max_s, quadratic_s, sum_array_s, merge_sort_s
1. Please show the order of programs and expected result in a text component above the PROG input.
3. In order to make your programs runnable on your processor you must do the following:
1. You will add an assembly language main to set up the parameters for your functions
2. You will add the end marker (add r0, r0, #0) to indicate when the program should stop
3. Ensure that you do not have .global or .func directives in your programs
4. Your processor implementation will include the following major sub-circuits:
1. The Program Counter (PC) will be one 32-bit register
2. Machine code instructions will be stored in a ROM component, just as we did in Project05. Like in Project05 your instruction memory will be able to select the program you want to execute.
3. The Arithmetic Logic Unit (ALU) will perform data processing tasks such as add, sub, mul, and mov.
Syllabus Schedule Assignments
https://cs315.cs.usfca.edu/projects/project06
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1202 llaF – 513 SC

2021/8/23 , , , CS 315 – Fall 2021 – Project06
4. The Sign Extension Unit will perform sign Seyxltlaebnussion, mScuhcehdluikle youAdssidignments when calculating branch offsets in Project04
5. Data Memory. We will use a RAM component to hold data on the simulated stack. We will not simulate any cache or dynamic memory.
6. The Control Unit will decode machine code instructions. As with Project05, the Control Unit will be the most complex part.
7. The Data Path will connect data between the various sub-circuits
8. The Control Path will connect the Control unit to various sub-circuits and multiplexers
Given
1. We will discuss the major sub-circuits in lecture and you will have hands-on time to develop and ask questions
2. We have compiled an implementation guide for Project06, available in two parts in the Resources section of this web site.
Rubric
For interactive grading you should be able to run each of the tests below with the inputs given.
(12 points) fib_rec_s(10) = 55 (0x37)
(12 points) find_max(5, {2, 6, 3, 9, 1}) = 9
(12 points) quadratic_s(2, 4, 6, 8) = 36 (0x24)
(12 points) sum_array(5, {4, 8, 12, 16, 20}) = 60 (0x3C)
(12 points) merge_sort_s(5, {16, 4, 32, 2, 8}) = {32, 16, 8, 4, 2} (15 points) Interactive grading question #1
(15 points) Interactive grading question #2
(10 points) Neatness
Extra Credit
1. You must complete all of the Project06 spec above in order to earn extra credit points.
2. You can have until Thursday, May 19th at 11:59 PM to finish extra credit work.
https://cs315.cs.usfca.edu/projects/project06
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1202 llaF – 513 SC

2021/8/23 y, y CS 315 – Fall 2021 – Project06
3. For all options below (except the disassembler), you must provide a suitable test
program which demonstrates that your simulation works.
1 point options:
1. mvn instruction support
2. rsb instruction support
3. and, orr, eor instruction support
5 point options:
1. Implement support for the register form of str: str r0, [r1, r2].
2. Implement support for ldr and str with shift support, e.g., ldr r0, [r1, r2,
lsl #2].
3. Implement support for ldr and str with post-increment and write back support.
4. Conditional Execution support for all instructions such as data processing, mul, sdt, bl, and bx.
10 point options:
1. Block Data Transfer instruction support (ldm and stm). See section 4.11 in the ARM Instruction Set Reference.
2. Single Data Swap instruction support (swp). See section 4.12 in the ARM Instruction Set Reference.
3. Implement a real-time disassembler for you top-level processor circuit so that you can see the instruction that is executing in a Digital Terminal component with the instruction name and the register names.
Propose your own extra credit. Send a proposal to your instructor for consideration. We can determine if your proposal is worth extra credit and, if, so, the point value.
Syllabus
Schedule
Assignments
https://cs315.cs.usfca.edu/projects/project06
3/3
1202 llaF – 513 SC