Microprogram Design
Use ASM from Lecture 16 to design the Microprograms
See Symbolic/Binary Microprogram on next slide
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 1
Symbolic/Binary Microprogram
This is not our control memory but similar
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 2
Indirect Instruction ASM
R32¡ûM[R[SA]]
R[DR]¡ûM[R32]
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 3
Right-Shift Instruction ASM
0
IR=00000111?
1
SRM1
00000111
R32¡ûzf IR[4:0]
1
zf IR[4:0]=0?
The number of shifts to the right n must be the same as the SB register that holds the value that will be shifted by n bits to the right
SRM2 SRM3
0
10000111
DR = SB
and
SB = Address = n sr
R[DR]¡ûsr R[SB]
R32¡ûR32-1
R32=0?
0
10001000
1
To IF
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 4
Hardwired Multiple-Cycle Control
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 5
Hardwired Control Unit
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 6
Pipelined (based on single-cycle)
Instruction Fetch
Decode and Operand Fetch
Execution
Write-back
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 7
Pipelined Execution Pattern
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 8
Computer Architecture and Microprocessor Systems
PL 1 PI 1
24 ZCNZVC10
Next Address MC 1
32
10
Instruction Address
PC
IR Opcode |DR|SA|SB
Extend
32
555
DR SA SB
RW TD||DR 1+5 TA||SA 1+5
D
(32+1) x 32 Register file
AB
IL
3
1
MS
17
1
32
V
1+5 TB||SB Data Address
76543210 MUX S
01 MUX C
10 MUX B
17
4
MW
RV || RC || RN || RZ
Reset
Bus A
1 MB
MM
Bus B
1
32 1 32
1
17
C1 4N1
Control Memory (2^17) x 42
Sequence Control Datapath Control
Zero Fill
32
32
AB
Function Unit
F
01 MUX M
CAR
V – C – N – Z
Data In Address
(2^32) x 32 Memory M
Data Out
Z
FS
1 1 5
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
NMMIPP TTTMFMRMMRRRRF ASCLILDABBSDWMWVCNZL
FL
32
Data
Instructions
MD
1 Bus D
01 MUX D
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 9