Multiple-Cycle Microprogrammed Computer
PL 1 PI 1
24 ZCNZVC10
Next Address MC 1
32
10
Instruction Address
PC
IR Opcode |DR|SA|SB
Extend
32
555
DR SA SB
RW TD||DR 1+5 TA||SA 1+5
D
(32+1) x 32 Register file
AB
IL
3
1
MS
17
1
32
V
1+5 TB||SB Data Address
76543210 MUX S
01 MUX C
10 MUX B
17
4
MW
RV || RC || RN || RZ
Reset
Bus A
1 MB
MM
Bus B
1
32 1 32
1
17
C1 4N1
1 1 5
Control Memory (2^17) x 42
Sequence Control Datapath Control
Zero Fill
32
32
AB
Function Unit
F
01 MUX M
CAR
V – C – N – Z
Data In Address
(2^32) x 32 Memory M
Data Out
Z
FS
FL ASCLILDABBSDWMWVCNZL BusD
32
Data
Instructions
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
NMMIPP TTTMFMRMMRRRRF
MD
1
01 MUX D
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 1
Project 2
Microcoded Instruction Set Processor
Project 2 in incremental steps
modifications are required:
Increase the number of registers in the register-file from 32 to 33
This requires an additional select bit for the two multiplexers (Bus A and Bus B) and the destination decoder. These are separate signals (TD, TA, TB) that are provided by the Control Memory
The size of the registers in the register-file has to be 32 bit (size of instructions)
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 2
Datapath Modifications
Consequently, all components of the Datapath: MUXs in the Register file
Decoder in the Register file Arithmetic/logic Unit
Shifter and MUXs …
are 32 bit
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 3
Datapath Modifications
Add and test:
Memory M (512 x 32) Control Memory (256 x 42)
to your project.
MUX M will feed 32 bit addresses from ether the Bus A or the PC into the Memory M entity but only the 9 least significant address bits will be used to index into the array. This restricts the memory size to 512.
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 4
Control Memory 256 x 42 library IEEE
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
— Michael Manzke
— michael.manzke@cs.tcd.ie
— 3rd December 2020
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 5
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
entity control_memory is
Port (FL
: out std_logic;
RZ : out std_logic;
RN : out std_logic;
RC : out std_logic;
RV : out std_logic;
MW : out std_logic;
MM : out std_logic;
RW : out std_logic;
MD : out std_logic;
FS : out std_logic_vector(4 downto 0); — 9 to 13
MB : out std_logic;
TB : out std_logic;
TA : out std_logic;
TD : out std_logic;
PL : out std_logic;
PI : out std_logic;
IL : out std_logic;
MC : out std_logic;
MS : out std_logic_vector(2 downto 0);
NA : out std_logic_vector(16 downto 0); IN_CAR : in std_logic_vector(16 downto 0));
–0 –1 –2 –3 –4
— 5 –6 –7 –8
— 14
— 15
— 16
— 17
— 18
— 19
— 20
— 21
— 22
— 25
to 24 to 41
end control_memory;
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 6
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
architecture Behavioral of control_memory is
type mem_array is array(0 to 255) of std_logic_vector(41 downto 0);
begin
memory_m: process(IN_CAR)
variable control_mem : mem_array:=(
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0| — | Next Address | MS | M| I| P| P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F| — | Next Address | MS | C| L| I| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
“00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–00 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–01 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–02 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–03 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–04 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–05 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–06 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–07
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 7
— Address $08 to $17
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0| — | Next Address | MS | M| I| P| P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F| — | Next Address | MS | C| L| I| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
“00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–08 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–09 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–0A “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–0B “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–0C “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–0D “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–0E “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–0F
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0| — | Next Address | MS | M| I| P| P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F| — | Next Address | MS | C| L| I| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
“00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–10 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–11 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–12 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–13 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–14 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–15 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–16 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–17
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 8
— Address $F8 to $FF
• • •
— |41 25|2422|21|20|19|18|17|16|15|14|13 9|8|7|6|5|4|3|2|1|0| — | Next Address | MS | M| I| P| P| T| T| T| M| FS |M|R|M|M|R|R|R|R|F| — | Next Address | MS | C| L| I| L| D| A| B| B| FS |D|W|M|W|V|C|N|Z|L|
“00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–F8 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–F9 “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–FA “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–FB “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–FC “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–FD “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–FE “00000000000000000000 0 0 0 0 0 0 0 000000000000000″,–FF
);
variable addr : integer;
variable control_out : std_logic_vector(41 downto 0);
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 9
Begin (process) LSB
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
begin
addr := conv_integer(IN_CAR);
control_out := control_mem(addr);
FL <= control_out(0);
RZ <= control_out(1);
RN <= control_out(2);
RC <= control_out(3);
RV <= control_out(4);
MW <= control_out(5);
MM <= control_out(6);
RW <= control_out(7);
MD <= control_out(8);
FS <= control_out(13 downto 9);
MB <= control_out(14);
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 10
Begin (process) MSB
44333333333322222 10987654321098765
Next Address
222 432
MS
22 10 MI CL
1 9 P I
1 8 P L
1 7 T D
1
6
T A
1 5 T B
111119 43210
M B
FS
87654
MRMMR DWMWV
3
R C
2
R N
1
R Z
0
F L
TB <= control_out(15);
TA <= control_out(16);
TD <= control_out(12);
PL <= control_out(17);
PI <= control_out(19);
IL <= control_out(20);
MC <= control_out(21);
MS <= control_out(24 downto 22);
NA <= control_out(41 downto 25);
end process;
end Behavioral;
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 11
VHDL top-level models
The Modified register-file The Functional Unit
The two memories
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 12
Block Diagram
PL 1 PI 1
24 ZCNZVC10
Next Address MC 1
32
10
Instruction Address
PC
IR Opcode |DR|SA|SB
Extend
32
555
DR SA SB
RW TD||DR 1+5 TA||SA 1+5
D
(32+1) x 32 Register file
AB
IL
3
1
MS
17
1
32
V
1+5 TB||SB Data Address
76543210 MUX S
01 MUX C
10 MUX B
17
4
MW
RV || RC || RN || RZ
Reset
Bus A
1 MB
MM
Bus B
1
32 1 32
Control Memory (2^17) x 42
Sequence Control Datapath Control
Zero Fill
32
32
1
17
C1 4N1
1 1 5
AB
Function Unit
F
01 MUX M
CAR
V - C - N - Z
Data In Address
(2^32) x 32 Memory M
Data Out
Z
FS
FL ASCLILDABBSDWMWVCNZL BusD
32
Data
Instructions
17 3 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1
NMMIPP TTTMFMRMMRRRRF
MD
1
01 MUX D
CSU22022, 15th Lecture, Dr. M. Manzke, Page: 13