Purpose: To provide an introduction to structured programming using the C/C++ language.
CS 2506 Computer Organization II MIPS 1: Machine Language and SCD
You are permitted to work in pairs for this assignment! 1
You may work in pairs for this assignment. If you choose to work with a partner, make sure only one of you submits a
solution, and that you paste a copy of the Partners Template that contains the names and PIDs of both students at the
beginning of the file.
Prepare your answers to the following questions in a plain text file. Submit your file to the Curator system by the posted
deadline for this assignment. No other file formats, or late submissions will be accepted.
You will submit your answers to the Curator System (www.cs.vt.edu/curator) under the heading MIPS01.
All questions refer to the completed single-cycle datapath (SCD) design, reproduced below, which supports execution of
the following MIPS instructions: add, sub, and, or, slt, lw, sw, beq and j.
Figure 1
1. Consider the execution of the following assembly instruction on the datapath shown in Figure 1:
sw $t0 16($t1)
a) [10 points] Write the machine code that would represent this instruction. For the sake of grading, put spaces
between the fields of the instruction.
b) [5 points] When this instruction is executed, the jump target address will be computed by the given hardware,
even though this is not a jump instruction. Explain why the fact that the jump target address is computed does not
interfere with the correct execution of the sw instruction. Be precise.
1b
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http://www.cs.vt.edu/curator
CS 2506 Computer Organization II MIPS 1: Machine Language and SCD
You are permitted to work in pairs for this assignment! 2
2. [10 points] The given design includes two different Shift left 2 units, one used in computing the jump target address
and one used in computing the branch target address. Explain why it would be logically possible to include only one
such unit, and still execute the same set of instructions. Be precise.
3. Suppose that, due to a manufacturing error, the control line RegDst is always set to 1, and that we are attempting to
execute a lw instruction:
lw rt, imm(rs) # GPR[rt] <-- Mem[GPR[rs] + imm] a) [5 points] Explain why this error would seem to interfere with the execution of the given lw instruction. b) [10 points] Under what circumstances would the lw instruction be executed correctly, despite the error? Be precise. 4. [10 points] The funct bits for the supported R-type instructions are as follows: Instruction funct bits add 100000 sub 100010 and 100100 or 100101 slt 101010 Obviously, the ALU control unit must be prepared to deal with each of those inputs correctly. With the given design, could the ALU control unit ever receive a set of 6 bits that do not occur in the table above? If not, why not? If yes, why, and could that cause any problems? 5. [10 points] Consider the execution of the following lw instruction on the datapath shown in Figure 1: lw $t3, 8($s7) # GPR[$t3] <-- Mem[GPR[$s7] + 8] The value in $t3 will be read, and sent out by the Register unit, even though lw does not need that value. Explain why this does not cause any logical errors. 6. [20 points] Consider enhancing the datapath design in Figure 1 to implement the addi instruction: addi rt, rs, Immediate # GPR[rt] <-- GPR[rs] + Immediate Of course, the ADDI instruction is encoded as an I-format instruction: Describe how the addi instruction could be executed, with minimal changes to the datapath design in Figure 1. Be complete and specific. If existing hardware would need to be changes, say how. If new hardware would need to be added, say what that would be and how it would be linked to the given hardware. Describe how control signals would need to be set. Vague answers will not do well. immediate rt rs 001000 CS 2506 Computer Organization II MIPS 1: Machine Language and SCD You are permitted to work in pairs for this assignment! 3 7. [20 points] Consider enhancing the datapath design in Figure 1 to implement the jr instruction: jr rs # PC <-- GPR[rs] Oddly, perhaps, the JR instruction is encoded as an R-format instruction (we will ignore the hint field): Describe how the JR instruction could be executed, with minimal changes to the datapath design in Figure 1. Be complete and specific. If existing hardware would need to be changes, say how. If new hardware would need to be added, say what that would be and how it would be linked to the given hardware. Describe how control signals would need to be set. Vague answers will not do well. 001000 hint 00000 00000 rs 000000