2021/10/7 上午10:37 Assignment 1 (M1) – 2021
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Assignment 1 (M1) – 2021
2021/10/10
IN PROGRESS
Next Up: Submit Assignment
Unlimited A�empts Allowed
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Details
Last updated 4th Oct, 2021 (Version 0.3)
Due dates:
Milestone 1 (50%): A max 4 page report for parts A-B (to Assignment Milestone
1 (h�ps://canvas.sydney.edu.au/courses/36473/assignments/309171) )
Milestone 2 (50%): A max 3 page appendix to Milestone 1 for parts C-D (to Assignment
Milestone 2 (h�ps://canvas.sydney.edu.au/courses/36473/assignments/329883) ). This should not
duplicate anything in your Milestone 1 report.
Goals:
Use the knowledge gained from earlier labs to implement a complete single-cycle processor
which can execute a real program.
Implement a simple pipelined RISC-V processor.
Gain experience wri�ng technical reports.
Reports:
Your answer should be in the form of a report explaining your design, with suppor�ng
appendices containing code lis�ngs and simula�ons. The appendices don’t count in the page
limit.
Here (h�ps://canvas.sydney.edu.au/courses/36473/files/19566936?wrap=1)
(h�ps://canvas.sydney.edu.au/courses/36473/files/19566936/download?download_frd=1) and here
(h�ps://canvas.sydney.edu.au/courses/36473/files/19566944?wrap=1)
(h�ps://canvas.sydney.edu.au/courses/36473/files/19566944/download?download_frd=1) are two
examples of well-wri�en papers describing a RISC processor (you could following a similar style
for your report). Here (h�ps://canvas.sydney.edu.au/courses/36473/files/19566935?wrap=1)
(h�ps://canvas.sydney.edu.au/courses/36473/files/19566935/download?download_frd=1) is an
example of a poorly wri�en paper. Submit Assignment
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https://canvas.sydney.edu.au/courses/36473/files/19566936/download?download_frd=1
https://canvas.sydney.edu.au/courses/36473/files/19566944?wrap=1
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Your report should be in A4 IEEE format
(h�ps://www.ieee.org/conferences/publishing/templates.html
(h�ps://www.ieee.org/conferences/publishing/templates.html) ) with the default font sizes, and
organized under the following sec�on headings: Introduc�on, Background, Architecture, Results,
Discussion, Conclusion, References, Appendices.
Your assumed audience is an engineer that may not know the details of RISC-V.
Your assignment should be submi�ed online to the eLearning site as a single pdf file before the
due date.
You can use Verilog instead of VHDL if you are more comfortable with that language.
Include a full simulation and report on the number of cycles required to execute your
implementa�on.
Comment on whether your result is a good one and what could be done to further improve
performance.
You should assume that the reader is familiar computer architecture in general, but not
necessarily the the RISC-V instruc�on set or your architecture. You should also make your
report standalone from this assignment ques�on i.e. explain the problem and your approach in
your report.
If you don’t finish the en�re ques�on, s�ll report on your answer. Par�al marks will be awarded.
No extensions will be granted and penalty for a late submission is deduc�on of 5% of the
maximum mark for each calendar day a�er the due date. A�er ten calendar days late, a mark of
zero will be awarded.
Marks will be awarded in the following manner: 70% based on the clarity and detail of your report,
and 30% on the elegance and understandability of your VHDL code. You must clearly explain your
datapath and control in your report, and comment your VHDL code (include a lis�ng of all your
VHDL code as an Appendix). Here are some general marking criteria.
Item Fail Pass Credit Dis�nc�on High Dis�nc�on
Report Ideas are poorly
organized and use
of sec�ons
illogical. Overall
report
indecipherable.
Can be
understood
with difficulty.
Not well
organized.
Mostly well organized
and logical. Overall
report is
understandable.
Well
organized,
logical and
easy to follow.
Publishable in a
high quality
research
conference.
Design Clearly would
never work, major
conceptual gaps
evident and
design not
understandable.
There are
clearly missing
parts to the
design and
minor
The lis�ngs and
simula�ons mostly
make sense, but it is
unclear whether or
not the goals were
achieved.
Design should
work and clear
evidence is
provided to
support the
results.
Clear and elegant
design supported
by artefacts such
as code lis�ngs
and simula�ons. Submit Assignment
https://www.ieee.org/conferences/publishing/templates.html
2021/10/7 上午10:37 Assignment 1 (M1) – 2021
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conceptual
gaps.
Individual Work
This assignment should be your own, individual work, i.e. you are not to share any of your work
with others.
You can use any code from earlier labs.
You can borrow ideas from other RISCV designs but your answer should only address the
problem at hand and must be based on the code used in the labs.
Turni�n will be used to detect similar reports or VHDL code. These will be treated as plagiarism
cases and formally reported to the University.
Student Ques�ons and Answers
1. Instruc�ons like “lw ra,12(sp)” requires a stack. Should we use data memory as a stack? (and in
this case, we need to ini�alise SP to the last address of dmem?) Or should we create a seperate
component? Do we care about stack overflows? Yes data memory should be used as a stack.
Using spike, you will be able to see where it ini�alises the SP and you can create memory which
works for the exis�ng program.
2. The assignment page says we need to submit both code and simula�on for Part A & B. Is the
simula�on refering to the testbench or the screenshot of modelsim simula�on waveforms? And
should we do in the testbench? just let the processor run for some clock cycles and check the
simula�on waveforms manually? The simula�on is the modelsim simula�on. You can create your
own testbench and it would be good if it runs the processor for a specified number of cycles and
checks the output.
3. What is the use of the given material (c files and makefile)? I think we would do the whole
assignment in VHDL? So, what is the point of giving these two files? They are so you can
change things if you like, e.g. you might want to change the input values to the taus() rou�ne
(see below). You may also want to modify the assembly file to insert pipeline bubbles in parts C
and D.
4. Is the lis�ng given in part A used to show what the IMEM for the assignment or does it have
another different use? Yes, it just illustrates how to get an assembly language lis�ng.
5. Ques�on A says show your working to get the output, are we do these by running the
simula�on of VHDL code? By “Modify the program so it computes taus()”, does it mean changes
the imem file? Yes, by running a Modelsim simula�on of the VHDL. To compute taus() you might
also want to change main().
6. Ques�on B says, “Implement a single cycle RISCV processor which can execute your answer to
Ques�on A”, does this mean that we do VHDL coding in part B while using another way in part
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A? It just means you create a single cycle processor which can execute the subrou�ne taus()
and compute the right answer for the inputs in part A.
7. From my understanding now, what we do is modify the C program to compute taus() for part A,
and based on the previous labs to create a processor which do the same job as the C program?
Correct.
8. If the above one is correct, do we have to run the C program on spike or can we use another
console? Please use spike so the results can be easily verified.
9. In the report of Milestone 1, do we also need to use the IEEE format or only in Milestone 2?
Only Milestone 2, Milestone 1 can be in any format.
If I use the IEEE format, do I s�ll need to separate the four parts, ABCD? Or just Introduc�on,
Background… to explain the en�re A-D ques�ons? You should cover ABCD somewhere in your
report but you don’t need specific sec�ons or to explicitly state the ques�ons.
10. Is there a limit on the number of words? Minimum or maximum. No minimum or maximum limit
but you need to stay within the font size and page limits specified.
11. I am about to start wri�ng the report for the assignment, and the requirement says the report
should be”organized under the following sec�on headings: Introduc�on, Background,
Architecture, Results, Discussion, Conclusion, References, Appendices.” I am not sure what
should be included in the discussion and conclusion part, could you post your explana�on on
the assignment page? That will be of great help for us. I have a collec�on of wri�ng resources at
h�p://phwl.org/wri�ng-resources (h�p://phwl.org/wri�ng-resources) . In par�cular, “Different
parts of reports (intro, results, conclusion etc):” is good.
12. What do instruc�ons like “lui a4,%hi(s0)” mean? These are op�misa�ons which are made by the
linker. The details are beyond the scope of this course but if you single step in spike, you will see
that they have been simplified. This is the “HINT” in Ques�on B. See below for single stepping
of _tausseed and then _taus.
# nm taus
00015a4c T _Balloc
00015af4 T _Bfree
…
000101ac T taus
0001019c T tausseed
000199cc T vfiprin�
…
# spike -d –isa=rv32i /opt/riscv32i/riscv32-unknown-elf/bin/pk taus
: un�l pc 0 0001019c
bbl loader
:
core 0: 0x000000000001019c (0x22a1a623) sw a0, 556(gp)
:
core 0: 0x00000000000101a0 (0x2201a423) sw zero, 552(gp)
:
core 0: 0x00000000000101a4 (0x2201a823) sw zero, 560(gp)
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:
core 0: 0x00000000000101a8 (0x00008067) ret
:
core 0: 0x0000000000010244 (0x00000413) li s0, 0
:
core 0: 0x0000000000010248 (0x00021937) lui s2, 0x21
:
core 0: 0x000000000001024c (0x01400493) li s1, 20
:
core 0: 0x0000000000010250 (0xf5dff0ef) jal pc – 0xa4
:
core 0: 0x00000000000101ac (0x22c1a783) lw a5, 556(gp)
:
core 0: 0x00000000000101b0 (0x00d79513) slli a0, a5, 13
:
core 0: 0x00000000000101b4 (0x00f54533) xor a0, a0, a5
:
core 0: 0x00000000000101b8 (0x01355513) srli a0, a0, 19
:
core 0: 0x00000000000101bc (0x00c79793) slli a5, a5, 12
: q
13. I am not sure how to achieve a call func�on in my own VHDL processor, can I do something like
insert the instruc�on for “taus” instead of that call? Your processor doesn’t need to explicitly do a
call. You just need to have code in memory which does the appropriate calls and change your test
bench to start execu�ng from the appropriate address, e.g. just remove the prin�() calls from main()
in the C program and start your processor execu�ng at the address of main().
14. Prin� isn’t in the imem at all however is in common. Is that the prin� we are meant to use and if
so are we to change the JAL command? I suggest you remove prin�() from main(). This is suggested
in the ques�on.
Ques�on A (Prerequsi�e for Milestone 1)
The assg21v1.tgz (h�ps://canvas.sydney.edu.au/courses/36473/files/19315092?wrap=1)
(h�ps://canvas.sydney.edu.au/courses/36473/files/19315092/download?download_frd=1)
(h�ps://canvas.sydney.edu.au/courses/36473/files/18070876/download?wrap=1) file uses the Tausworth
algorithm to generate pseudorandom numbers (as presented in Fig 3 of
h�p://phwl.org/assets/papers/bm_tc06.pdf (h�p://phwl.org/assets/papers/bm_tc06.pdf) if you want
to understand the theory, see this paper (h�ps://canvas.sydney.edu.au/courses/36473/files/19315060?
wrap=1) (h�ps://canvas.sydney.edu.au/courses/36473/files/19315060/download?download_frd=1) ).Submit Assignment
https://canvas.sydney.edu.au/courses/36473/files/19315092?wrap=1
https://canvas.sydney.edu.au/courses/36473/files/19315092/download?download_frd=1
https://canvas.sydney.edu.au/courses/36473/files/18070876/download?wrap=1
http://phwl.org/assets/papers/bm_tc06.pdf
https://canvas.sydney.edu.au/courses/36473/files/19315060?wrap=1
https://canvas.sydney.edu.au/courses/36473/files/19315060/download?download_frd=1
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It contains taus.c which is the source code. Typing “make taus.lst” will create taus.lst which is the file
below.
GAS LISTING taus.s page 1
1 .file “taus.c”
2 .option nopic
3 .text
4 .align 2
5 .globl tausseed
6 .type tausseed, @function
7 tausseed:
8 0000 B7070000 lui a5,%hi(s0)
9 0004 23A0A700 sw a0,%lo(s0)(a5)
10 0008 B7070000 lui a5,%hi(s1)
11 000c 23A00700 sw zero,%lo(s1)(a5)
12 0010 B7070000 lui a5,%hi(s2)
13 0014 23A00700 sw zero,%lo(s2)(a5)
14 0018 67800000 ret
15 .size tausseed, .-tausseed
16 .align 2
17 .globl taus
18 .type taus, @function
19 taus:
20 001c 37070000 lui a4,%hi(s0)
21 0020 83270700 lw a5,%lo(s0)(a4)
22 0024 1395D700 slli a0,a5,13
23 0028 3345F500 xor a0,a0,a5
24 002c 13553501 srli a0,a0,19
25 0030 9397C700 slli a5,a5,12
26 0034 B7E6FFFF li a3,-8192
27 0038 B3F7D700 and a5,a5,a3
28 003c 3345F500 xor a0,a0,a5
29 0040 2320A700 sw a0,%lo(s0)(a4)
30 0044 B7060000 lui a3,%hi(s1)
31 0048 83A70600 lw a5,%lo(s1)(a3)
32 004c 13972700 slli a4,a5,2
33 0050 3347F700 xor a4,a4,a5
34 0054 13579701 srli a4,a4,25
35 0058 93974700 slli a5,a5,4
36 005c 93F707F8 andi a5,a5,-128
37 0060 3347F700 xor a4,a4,a5
38 0064 23A0E600 sw a4,%lo(s1)(a3)
39 0068 37060000 lui a2,%hi(s2)
40 006c 83270600 lw a5,%lo(s2)(a2)
41 0070 93963700 slli a3,a5,3
42 0074 B3C6F600 xor a3,a3,a5
43 0078 93D6B600 srli a3,a3,11
44 007c B7050000 lui a1,%hi(b)
45 0080 23A0D500 sw a3,%lo(b)(a1)
46 0084 93971701 slli a5,a5,17
47 0088 B705E0FF li a1,-2097152
48 008c B3F7B700 and a5,a5,a1
49 0090 B3C7D700 xor a5,a5,a3
50 0094 2320F600 sw a5,%lo(s2)(a2)
51 0098 3345E500 xor a0,a0,a4
52 009c 3345F500 xor a0,a0,a5
53 00a0 67800000 ret
54 .size taus, .-taus
55 .align 2
56 .globl main
57 .type main, @function
GAS LISTING taus.s page 2
58 main:
59 00a4 130101FF addi sp,sp,-16
60 00a8 23261100 sw ra,12(sp)
61 00ac 23248100 sw s0,8(sp)
62 00b0 23229100 sw s1,4(sp)
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http://phwl.org/assets/papers/bm_tc06.pdf
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63 00b4 23202101 sw s2,0(sp)
64 00b8 3765BC00 li a0,12345344
65 00bc 1305E514 addi a0,a0,334
66 00c0 97000000 call tausseed
66 E7800000
67 00c8 13040000 li s0,0
68 00cc 37090000 lui s2,%hi(.LC0)
69 00d0 93044001 li s1,20
70 .L4:
71 00d4 97000000 call taus
71 E7800000
72 00dc 13060500 mv a2,a0
73 00e0 93050400 mv a1,s0
74 00e4 13050900 addi a0,s2,%lo(.LC0)
75 00e8 97000000 call printf
75 E7800000
76 00f0 13041400 addi s0,s0,1
77 00f4 E31094FE bne s0,s1,.L4
78 00f8 13050000 li a0,0
79 00fc 8320C100 lw ra,12(sp)
80 0100 03248100 lw s0,8(sp)
81 0104 83244100 lw s1,4(sp)
82 0108 03290100 lw s2,0(sp)
83 010c 13010101 addi sp,sp,16
84 0110 67800000 jr ra
85 .size main, .-main
86 .comm b,4,4
87 .comm s2,4,4
88 .comm s1,4,4
89 .comm s0,4,4
90 .section .rodata.str1.4,”aMS”,@progbits,1
91 .align 2
92 .LC0:
93 0000 2532643A .string “%2d: %08X\n”
93 20253038
93 580A00
94 .ident “GCC: (GNU) 8.2.0”
The assembly language was compiled from the C program below.
#include
unsigned s0, s1, s2, b;
// provide an initial seed to the random number generator
void tausseed(unsigned seed)
{
s0 = seed;
s1 = 0;
s2 = 0;
}
// return the next number in the sequence
unsigned taus()
{
/* Generates numbers between 0 and 1. */
b = (((s0 << 13) ^ s0) >> 19);
s0 = (((s0 & 0xFFFFFFFE) << 12) ^ b);
b = (((s1 << 2) ^ s1) >> 25);
s1 = (((s1 & 0xFFFFFFF8) << 4) ^ b);
b = (((s2 << 3) ^ s2) >> 11);
s2 = (((s2 & 0xFFFFFFF0) << 17) ^ b);
return s0 ^ s1 ^ s2;
}
int main()
{
tausseed(12345678U);
for (int i = 0; i < 20; i++)
printf("%2d: %08X\n", i, taus());
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return 0;
}
The Makefile has one input file: taus.c which contains a prin� to facilitate debugging in
spike.
You can verify correct opera�on of the program using :
# make
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -S -O1 -march=rv32i -mabi=ilp32 taus.c
/opt/riscv32i/riscv32-unknown-elf/bin/as --traditional-format -march=rv32i -mabi=ilp32 -al taus.s > t
aus.lst
rm -f a.out
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -O1 -march=rv32i -mabi=ilp32 -c -o taus.o taus.c
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -O1 -march=rv32i -mabi=ilp32 taus.o -o taus
rm -f taus.o
spike –isa=rv32i /opt/riscv32i/riscv32-unknown-elf/bin/pk taus
bbl loader
0: C614F192
1: 4F192B04
2: 92B04D4F
3: 04D4F363
4: 4F363357
5: 6335712B
6: 5712B9A2
7: 2B9A2004
8: A2004DF3
9: 04DF3577
10: F3577C4E
11: 77C4E39B
12: 4E39BD76
13: 9BD76F32
14: 76F32EC6
15: 32EC6265
16: C62657D4
17: 657D419B
18: D419B9A9
19: 9B9A9C65
The program prints the first 20 numbers in the pseudorandom sequence generated by the
Tausworthe random number generator. When running your modelsim simula�on (and spike
simula�ons for comparison) in later parts of the assignment, you can modify taus.c as your answer
does not need to support the prin�() func�on.
Modify the program so the ini�al seed passed to tausseed(S) is your student number (instead of
12345678U).
In your report, show your working to get the final value printed by the program (in the example with
the default seed, the answer is 0x9B9A9C65).
Ques�on B (100% of Milestone 1)
Implement a single cycle RISCV processor which can execute your answer to Ques�on A. Your
processor will need to implement a subset of the rv32i instruc�on set. Do not include anySubmit Assignment
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instruc�ons except those required (marks will be deducted for unneeded instruc�ons).
Write your own testbench to verify that the results are correct.
HINT: Note that the assembly lis�ng does not include all the resolved addresses. Instead, the linker,
is called a�er the assembler (look up “Linker” in the textbook) to do this. For example, if you single
step the “call” instruc�on of the program, you can find what address the linker resolves this to, and
this is different to the assembly lis�ng. Thus the best way to understand how the program works is
to single step in spike.
Ques�on C (70% of Milestone 2)
Modify your single cycle processor to implement a 2-stage pipelined processor where the first stage
is instruc�on fetch, register fetch and decode, and the second stage implements the execute,
memory and write back parts (your solu�on must use this exact arrangement). Moreover,
implement a sta�c branch predic�on scheme which assumes that backward branches will be taken
and that forward branches will not (see
h�ps://en.wikipedia.org/wiki/Branch_predictor#Sta�c_branch_predic�on
(h�ps://en.wikipedia.org/wiki/Branch_predictor#Sta�c_branch_predic�on) ). A suggested datapath for this
ques�on is given below.
To help with this ques�on, here is the assembly language input (taus.s) which you can
modify if necessary to resolve RAW hazards by adding NOP instruc�ons.
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.file “taus.c”
.option nopic
.text
.align 2
.globl tausseed
.type tausseed, @function
tausseed:
lui a5,%hi(s0)
sw a0,%lo(s0)(a5)
lui a5,%hi(s1)
sw zero,%lo(s1)(a5)
lui a5,%hi(s2)
sw zero,%lo(s2)(a5)
ret
.size tausseed, .-tausseed
.align 2
.globl taus
.type taus, @function
taus:
lui a4,%hi(s0)
lw a5,%lo(s0)(a4)
slli a0,a5,13
xor a0,a0,a5
srli a0,a0,19
slli a5,a5,12
li a3,-8192
and a5,a5,a3
xor a0,a0,a5
sw a0,%lo(s0)(a4)
lui a3,%hi(s1)
lw a5,%lo(s1)(a3)
slli a4,a5,2
xor a4,a4,a5
srli a4,a4,25
slli a5,a5,4
andi a5,a5,-128
xor a4,a4,a5
sw a4,%lo(s1)(a3)
lui a2,%hi(s2)
lw a5,%lo(s2)(a2)
slli a3,a5,3
xor a3,a3,a5
srli a3,a3,11
lui a1,%hi(b)
sw a3,%lo(b)(a1)
slli a5,a5,17
li a1,-2097152
and a5,a5,a1
xor a5,a5,a3
sw a5,%lo(s2)(a2)
xor a0,a0,a4
xor a0,a0,a5
ret
.size taus, .-taus
.align 2
.globl main
.type main, @function
main:
addi sp,sp,-16
sw ra,12(sp)
sw s0,8(sp)
sw s1,4(sp)
sw s2,0(sp)
li a0,12345344
addi a0,a0,334
call tausseed
li s0,0
lui s2,%hi(.LC0)
li s1,20
.L4:
call taus
mv a2,a0
mv a1,s0
addi a0,s2,%lo(.LC0)
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2021/10/7 上午10:37 Assignment 1 (M1) – 2021
https://canvas.sydney.edu.au/courses/36473/assignments/309171 11/13
Academic honesty
While the University is aware that the vast majority of students and staff act ethically and honestly, it
is opposed to and will not tolerate academic dishonesty or plagiarism and will treat all allegations of
dishonesty seriously.
Further information on academic honesty, academic dishonesty, and the resources available to all
students can be found on the academic integrity pages on the current students website:
https://sydney.edu.au/students/academic-integrity.html (https://sydney.edu.au/students/academic-
integrity.html) .
Further information for on research integrity and ethics for postgraduate research students and
students undertaking research-focussed coursework such as Honours and capstone research
projects can be also be found on the current students website:
https://sydney.edu.au/students/research-integrity-ethics.html
(https://sydney.edu.au/students/research-integrity-ethics.html) .
call printf
addi s0,s0,1
bne s0,s1,.L4
li a0,0
lw ra,12(sp)
lw s0,8(sp)
lw s1,4(sp)
lw s2,0(sp)
addi sp,sp,16
jr ra
.size main, .-main
.comm b,4,4
.comm s2,4,4
.comm s1,4,4
.comm s0,4,4
.section .rodata.str1.4,”aMS”,@progbits,1
.align 2
.LC0:
.string “%2d: %08X\n”
.ident “GCC: (GNU) 8.2.0”
Ques�on D (30% of Milestone 2)
Add at least one type of forwarding to your Ques�on C solu�on to reduce the number of cycles in
your implementa�on. You do not need to implement this in RTL, however, you should give a
detailed descrip�on of the datapath and control changes needed in your report. Also include an
simula�on (or es�mate) to show how many cycles the branch predic�on in Ques�on C and
forwarding will save in the execu�on of the Tausworthe generator. Note that the other benefit of
pipelining is higher clock rate which we do not consider in this lab (you should men�on this in your
report).
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https://sydney.edu.au/students/academic-integrity.html
https://sydney.edu.au/students/research-integrity-ethics.html
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https://canvas.sydney.edu.au/courses/36473/assignments/309171 12/13
Compliance statement
In submitting this work, I acknowledge I have understood the following:
I have read and understood the University of Sydney’s Academic Honesty in Coursework
Policy 2015 (https://sydney.edu.au/policies/showdoc.aspx?recnum=PDOC2012/254&RendNum=0) .
The work is substantially my own and where any parts of this work are not my own I have
indicated this by acknowledging the source of those parts of the work and enclosed any quoted
text in quotation marks.
The work has not previously been submitted in part or in full for assessment in another unit unless
I have been given permission by my unit of study coordinator to do so.
The work will be submitted to similarity detection software (Turnitin) and a copy of the work will be
retained in Turnitin’s paper repository for future similarity checking. Note: work submitted by
postgraduate research students for research purposes is not added to Turnitin’s paper repository.
Engaging in plagiarism or academic dishonesty in coursework will, if detected, lead to the
University commencing proceedings under the Academic Honesty in Coursework Policy 2015
(https://sydney.edu.au/policies/showdoc.aspx?recnum=PDOC2012/254&RendNum=0) and the
Academic Honesty Procedures 2016 (http://sydney.edu.au/policies/default.aspx?
mode=glossary&word=Academic+honesty) .
Engaging in plagiarism or academic dishonesty in research-focussed work will lead to the
University commencing proceedings under the Research Code of Conduct 2013
(https://sydney.edu.au/policies/showdoc.aspx?recnum=PDOC2013/321&RendNum=0) and the
Academic Honesty Procedures 2016 (http://sydney.edu.au/policies/default.aspx?
mode=glossary&word=Academic+honesty) .
Engaging another person to complete part or all of the submitted work will, if detected, lead to the
University commencing proceedings against me for potential student misconduct under the
University of Sydney (Student Discipline) Rule 2016
(http://sydney.edu.au/policies/showdoc.aspx?recnum=PDOC2017/441&RendNum=0) .
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https://sydney.edu.au/policies/showdoc.aspx?recnum=PDOC2012/254&RendNum=0
https://sydney.edu.au/policies/showdoc.aspx?recnum=PDOC2012/254&RendNum=0
http://sydney.edu.au/policies/default.aspx?mode=glossary&word=Academic+honesty
https://sydney.edu.au/policies/showdoc.aspx?recnum=PDOC2013/321&RendNum=0
http://sydney.edu.au/policies/default.aspx?mode=glossary&word=Academic+honesty
http://sydney.edu.au/policies/showdoc.aspx?recnum=PDOC2017/441&RendNum=0
https://api.turnitin.com/api/lti/1p0/user/static_eula
2021/10/7 上午10:37 Assignment 1 (M1) – 2021
https://canvas.sydney.edu.au/courses/36473/assignments/309171 13/13
This assignment submission is my own, original work
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