CS计算机代考程序代写 chain COMP3222/9222 Digital Circuits & Systems

COMP3222/9222 Digital Circuits & Systems
5. Flip-flops, Registers, Counters

Objectives
• Learn about logic circuits that store information

– Flip-flops that store a single bit
– Registers that store multiple bits
– Shift registers that shift the contents of the register
– Counters of various types

• VHDL constructs used to implement storage elements

20T3 COMP3222/9222 Flip-flops L05/S2

Memory
element Alarm

Sensor

Reset

Set
On Off ⁄

Why we need circuits with memory
• Consider an alarm system that is required to remain

activated when triggered, even when the cause for
triggering has ceased

• Here, the Reset signal is intended to provide a means of
switching off the alarm

20T3 COMP3222/9222 Flip-flops L05/S3

• Use feedback to “trap” a value
• Consider a simple cyclic circuit comprising two inverters

• The circuit has two stable states
• But there is no way of changing from one state to the

other

A B

How do we create a memory element?

1 00 1

20T3 COMP3222/9222 Flip-flops

A
10

L05/S4

A B
OutputData

Load

TG1

TG2

0 = preserve current state1 = load new state

A controlled memory element

A B
OutputData

Load

TG1

TG2

0 1
01

1 0
1

0 = preserve current state

20T3 COMP3222/9222 Flip-flops L05/S5

A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0

Reset

Set Q

A memory element with NOR gates

• When both Set and Reset are 0, the state, Q, is
preserved

• Set = 1, Reset = 0 Þ Q = 1
• Set = D, Reset = 1 Þ Q = 0
• Known as a latch

0 Q’1 0 10 1 0

20T3 COMP3222/9222 Flip-flops L05/S6

Basic latch using cross-coupled NOR gates
S R Qa Qb

0 0
0 1
1 0
1 1

0/1 1/0
0 1
1 0
0 0

(a) Conventional
circuit diagram

(b) Characteristic table

Time

Q a

Q b

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

(no change)
Reset

Set Q

Oscillatory
behaviour which
settles to a final
state that
depends upon
the relative
speed of gates
and wires

20T3 COMP3222/9222 Flip-flops(c) Timing diagram L05/S7

Gated SR latch
• A control input (Clk) acts to enable state changes

Illegal input
condition as
outputs are
supposed to be
complements of
each other

20T3 COMP3222/9222 Flip-flops L05/S8

Clk

Gated SR latch with NAND gates
• More usual configuration as it uses less transistors

– Has exactly the same characteristic table
– Note that S & R inputs are flipped about wrt the outputs

20T3 COMP3222/9222 Flip-flops

A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0 L05/S9

Gated D latch
• Eliminates the illegal input combination S = R = 1
• Useful for storing a data bit

20T3 COMP3222/9222 Flip-flops

latches are said to be
“transparent” to changes
in the data input while the
Clk input is high

L05/S10

Clock

Q m

Q Q s =

D Q

Master Slave

Clock

Q m Q s

(a) Circuit

D Q

Q Clk

D Q

Q Clk

Negative edge-triggered (Master-slave)
D flip-flop
• Latches are triggered by the level of the control signal,

flip-flops are triggered on control signal transitions

Master
active

Slave active

Input stored

20T3 COMP3222/9222

D Q

Q Clk

D Q

Q Clk

D Q

Q Clk

D Q

Q Clk

Flip-flops(b) Timing diagram L05/S11

Clock

(a) Circuit

D Q

(b) Graphical symbol

Clock

A positive-edge-triggered D flip-flop
We could just invert the Clk input to
the Master latch and feed the Clk
signal straight through to the Slave,
but the arrangement presented here
saves two NAND gates and one inverter

D’

® 1

® D’

® D

if D =0 when
Clock , P2 = 0
keeps P4 at 1,
irrespective of
subsequent
changes to D
while Clock high

if D = 1 when
Clock , P1 = 0
keeps P2 & P3
at 1, irrespective
of subsequent
changes to D
while Clock high

20T3 COMP3222/9222

® D

L05/S12

Comparison of level-sensitive
and edge-triggered D-type storage elements

D Q

Clock Q a

Q b

Q c

Q b

Q a

(a) Circuit

Clk

Clock

Q a

Q b

(b) Timing diagram

Q c

20T3 COMP3222/9222 Flip-flops L05/S13

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY implied IS
PORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;
END implied ;

ARCHITECTURE Behavior OF implied IS
BEGIN

PROCESS ( A, B )
BEGIN

IF A = B THEN
AeqB <= '1' ; END IF ; END PROCESS ; END Behavior ; Recall the specification of implied memory Resulting circuit has to remember the value of AeqB when A /= B 20T3 COMP3222/9222 Flip-flops 1 0 1 A B AeqB A B AeqB L05/S14 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, CLK : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ; ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D, CLK ) BEGIN IF CLK = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Code for a gated D latch 20T3 COMP3222/9222 Flip-flops Note: the PROCESS describing a latch, while exploiting implicit memory, complies with the COMBINATIONAL design rule that all signals that can affect the output are listed in the sensitivity list L05/S15 The signal attribute ‘event is true when the signal transitions from one level to another LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, CLK : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( CLK ) BEGIN IF CLK’event AND CLK = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Code for a positive edge-triggered D flip-flop D Clock Q 20T3 COMP3222/9222 Flip-flops Notes: (i) SYNCHRONOUS PROCESSes only list the clock signal in the sensitivity list; (ii) All assignment statements within a synchronous process should be guarded by a (CLK’event AND CLK=‘ ’) condition; (iii) Each signal on the LHS of an assignment statement guarded by a (CLK’event AND CLK=‘ ’) condition is the output of a flip-flop L05/S16 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior ; Equivalent code using a WAIT UNTIL statement When used for the synthesis of a synchronous circuit, the WAIT UNTIL statement must be the first in a PROCESS block; all assignment statements that follow infer a flip-flop 20T3 COMP3222/9222 Flip-flops L05/S17 Q Q D Clock (a) Circuit D Q Q Preset Clear (b) Graphical symbol Clear Preset Master-slave D flip-flop with Clear and Preset • A design may call for a preset value on a FF • Active low Preset’ and Clear’ inputs allow the flip-flop to be set to a given value asynchronously (indepen- dently of the Clock) – only one of them should be pulled low at a time • How long does the FF stay in the Clear or Preset state? 20T3 COMP3222/9222 Flip-flops 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 L05/S18 Positive-edge-triggered D flip-flop with Clear and Preset ~Preset forces this node low when Clk high ~Clear forces this node low when Clk high 20T3 COMP3222/9222 Flip-flops L05/S19 Positive-edge-triggered D flip-flop with synchronous Clear and Preset • Synchronous clear and preset is best done by gating the D input 20T3 COMP3222/9222 Flip-flops L05/S20 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, CLK : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, CLK ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF CLK'EVENT AND CLK = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; D flip-flop with asynchronous reset 20T3 COMP3222/9222 Flip-flops Notes: (i) For a synchronous process with an asynchronous reset/set, both the CLK and the reset/set signal must be in the sensitivity list. (ii) Only assign a constant, e.g. ‘0’/‘1’, to the FF output within the reset/set condition. L05/S21 D flip-flop with synchronous reset Question: How do you specify this behaviour using an IF statement? LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock’EVENT AND Clock = ‘1’; IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ; END Behavior ; Flip-flops L05/S22 Code for an eight-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS (Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= “00000000” ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; 20T3 COMP3222/9222 Flip-flops L05/S23 Code for an n-bit register with asynchronous clear Parameterized component with default value of 16 for the data width parameter N Idiom for setting all bits of a signal to 0s LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ); PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= (OTHERS => ‘0’) ;

ELSIF Clock’EVENT AND Clock = ‘1’ THEN
Q <= D ; END IF ; END PROCESS ; END Behavior ; Flip-flops L05/S24 8-bit register based on regn component LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clk : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Structure OF reg8 IS BEGIN reg8: regn Assumes regn component GENERIC MAP ( N => 8 ) declared in the working
PORT MAP ( D, Resetn, Clk, Q); directory

END Structure ;
GENERIC MAP used to
overwrite default parameter
value

20T3 COMP3222/9222 Flip-flops L05/S25

D Q

Q Clock

D Q

In Out

t 1 0 1 0 0 0

t 2 1 0 1 0 0

t 3 1 1 0 1 0

t 4 1 1 1 0 1

t 5 0 1 1 1 0

t 6 0 0 1 1 1

t 7 0 0 0 1 1

t 0 1 0 0 0 0

Q 1 Q 2 Q 3 Q 4 Out = In

Q 1 Q 2 Q 3 Q 4

A simple shift register

0
1

0 0 0 01 10 101 1 0 11 0 11 00 0 10

20T3 COMP3222/9222 Flip-flops L05/S26

Parallel-access shift register
Q 3 Q 2 Q 1 Q 0

Clock
Parallel input

Parallel output

Shift/LoadSerialinput

D Q

20T3 COMP3222/9222 Flip-flops

2-to-1
MUX

L05/S27

Behavioural code for a D flip-flop with a 2-to-1
multiplexer on the D input
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY muxdff IS
PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ;
END muxdff;

ARCHITECTURE Behavior OF muxdff IS
BEGIN

PROCESS
BEGIN

WAIT UNTIL Clock’EVENT AND Clock = ‘1’;
IF Sel = ‘0’ THEN

Q <= D0 ; ELSE Q <= D1 ; END IF ; END PROCESS ; END Behavior ; Flip-flops -- or: -- PROCESS (Clock) -- BEGIN -- IF Clock’ … THEN -- IF Sel … -- etc. -- END IF; -- END IF; L05/S28 • Design hierarchies are recursive structures comprised of components, or sub-circuits, whose architectures, at the leaf level, are expressed in terms of their behaviours Hierarchical code for a four-bit shift register LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shift4 IS PORT ( P : IN STD_LOGIC_VECTOR( 3 DOWNTO 0) ; ser, ld, Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) ) ; END shift4; ARCHITECTURE Structure OF shift4 IS COMPONENT muxdff PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END COMPONENT; BEGIN Stage3: muxdff PORT MAP ( ser, P(3), ld, Clock, Q(3) ); Stage2: muxdff PORT MAP ( Q(3), P(2), ld, Clock, Q(2) ); Stage1: muxdff PORT MAP ( Q(2), P(1), ld, Clock, Q(1) ); Stage0: muxdff PORT MAP ( Q(1), P(0), ld, Clock, Q(0) ); END Structure ; Q3 Q2 Q1 Q0 ClockParallel input Parallel output Shift/LoadSerialinput D Q Q D Q Q D Q Q D Q Q BUFFER mode allows Q to be used in both IN and OUT modes Flip-flops Alternative (behavioural) code for a shift register 20T3 COMP3222/9222 1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY shift4 IS 4 PORT ( P : IN STD_LOGIC_VECTOR( 3 DOWNTO 0) ; 5 ser, ld, Clock : IN STD_LOGIC ; 6 Q : BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) ) ; 7 END shift4; 8 ARCHITECTURE Behavior OF shift4 IS 9 BEGIN 10 PROCESS 11 BEGIN 12 WAIT UNTIL Clock’EVENT AND Clock = ‘1’ ; 13 IF ld = ‘1’ THEN 14 Q <= P ; 15 ELSE 16 Q(0) <= Q(1) ; 17 Q(1) <= Q(2) ; 18 Q(2) <= Q(3) ; 19 Q(3) <= ser ; 20 END IF ; 21 END PROCESS ; 22 END Behavior ; A WAIT UNTIL statement implies all signals assigned a value inside the process are implemented as the output of a flip-flop BUFFER mode allows Q to appear on both the left and right sides of signal assignments Flip-flops L05/S30 20T3 COMP3222/9222 1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY shift4 IS 4 PORT ( P : IN STD_LOGIC_VECTOR( 3 DOWNTO 0) ; 5 ser, ld, Clock : IN STD_LOGIC ; 6 Q : BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) ) ; 7 END shift4; 8 ARCHITECTURE Behavior OF shift4 IS 9 BEGIN 10 PROCESS 11 BEGIN 12 WAIT UNTIL Clock’EVENT AND Clock = ‘1’ ; 13 IF ld = ‘1’ THEN 14 Q <= P ; 15 ELSE 16 Q(3) <= ser ; 17 Q(2) <= Q(3) ; 18 Q(1) <= Q(2) ; 19 Q(0) <= Q(1) ; 20 END IF ; 21 END PROCESS ; 22 END Behavior ; Flip-flops IMPORTANT: Why is the statement order immaterial? Identical code, which reverses the ordering of statements 16 – 19 in L05/S30 L05/S31 Code for an n-bit left-to-right shift register Just as the FOR…GENERATE statement is used to generate a set of concurrent statements, the FOR…LOOP statement is used to generate a set of sequential statements 1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 ENTITY shiftn IS 4 GENERIC ( N : INTEGER := 8 ) ; 5 PORT ( P : IN STD_LOGIC_VECTOR( N-1 DOWNTO 0) ; 6 ser, ld, Clock : IN STD_LOGIC ; 7 Q : BUFFER STD_LOGIC_VECTOR( N-1 DOWNTO 0) ) ; 8 END shiftn; 9 ARCHITECTURE Behavior OF shiftn IS 10 BEGIN 11 PROCESS 12 BEGIN 13 WAIT UNTIL Clock’EVENT AND Clock = ‘1’ ; 14 IF ld = ‘1’ THEN 15 Q <= P ; 16 ELSE 17 Genbits: FOR i IN 0 to N-2 LOOP 18 Q(i) <= Q(i+1) ; 19 END LOOP ; 20 Q(N-1) <= ser ; 21 END IF ; 22 END PROCESS ; 23 END Behavior ; 20T3 COMP3222/9222 Flip-flops L05/S32 Flip-flop timing parameters • Three important parameters that need to be considered in the design of sequential circuits: – Propagation delay, tcQ, the time needed for the output of the FF to change after the triggering clock edge has occurred – Setup time, tsu, the time interval the input needs to be stable for prior to the triggering clock edge, for it to be reliably read – Hold time, th, the time interval the input needs to be stable for after the triggering clock edge, for it to be reliably read • The magnitude of these parameters depend upon the design of the flip-flop, the process technology used to implement them, and the source voltage 20T3 COMP3222/9222 Flip-flops L05/S33 Propagation delay tcQ (propagation delay) may not be the same for 0 ® 1 and 1 ® 0 transitions, and is usually specified using min and max values • Propagation delay is the time it takes for the new value to emerge from a flip-flop after the triggering edge 20T3 COMP3222/9222 Flip-flops L05/S34 tcQ for a gated D latch 20T3 COMP3222/9222 1 1 1 1 0 0 →10 → 0 △ →1 2△ → 0 3△ 0 0 1 1 0 →10 → 0 △ 0 →1 2△ 1 → 0 3△ 1 Flip-flops Here, tcQ is 2△ for 0→1 transitions, but 3△ for 1→0 transitions L05/S35 • The designer of the circuit that generates the D signal must ensure setup and hold times are satisfied • Together, they define a window of time around the triggering clock edge during which D must be stable • Typical values for 28nm CMOS are tsu = 0.03 ns and th = 0.02 ns t su t h Clk D Q t su tsuÞ a change in D has to have had time to be seen at the outputs before the negative Clk edge 20T3 COMP3222/9222 Flip-flops L05/S36 Setup and hold times D Clock N4 N1 N2 N3 5 6 1 2 3 (a) Circuit D Q Q (b) Graphical symbol Clock Q Q 4 Recall positive-edge-triggered D flip-flop 0 1 1 D’ D ® 1 ® D’ ® D’ ® D if D = 1 when Clock , N2 = 0 keeps N1 & N3 at 1, irrespective of subsequent changes to D while Clock high 20T3 COMP3222/9222 ® D Flip-flops L05/S37 D Clock 5 6 1 2 3 Q Q 4 th for a positive-edge-triggered D flip-flop 20T3 COMP3222/9222 D Clk N1 N2 N3 N4 N5 N6 t=0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 △2 △2+△5 △2+△5+△6 held hi after △2+△3 (a) Normal operation D Clk N1 N2 N3 N4 N5 N6 t=0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 e e +△4 e +△4+△3 e +△4+△1 if △2 > e +△4+△1

(b) Hold time violation

held hi after △2+△1

Flip-flops L05/S38

The larger 𝜀 is,
the less likely it
is for N2 to be
held high

T flip-flop

Clock

T Q

(b) Graphical symbol

D Q

Q
T

Clock

(a) Circuit

20T3 COMP3222/9222

0
1

Q t 1 + ( )

Q t ( )
Q t ( )

(d) Characteristic table

Q(t+1) = T.Q’(t) + T’.Q(t)
= T XOR Q(t)

(e) Characteristic equation:

L05/S39

D Q

Clock

(a) Circuit

J Q

(b) Graphical symbol

K
0
1

Q t 1+( )
Q t( )
0

J
0
0

0 11
1 Q t( )1

JK flip-flop
• Combines the features of an SR flip-flop and a T flip-flop

L05/S40

T Q

Q Clock

T Q

Q 0 Q 1 Q 2

Clock

Q 0

Q 1

Q 2

Count 0 1 2 3 4 5 6 7 0
Timing diagram

A three-bit up-counter (ripple counter)

The ripple effect of the triggering edge due to tcQ propagation
delays causes glitching from 011 ® 010 ® 000 ® 100

0
1

Q t 1 + ( )

Q t ( )
Q t ( )

Characteristic table

20T3 COMP3222/9222 Flip-flops L05/S41

T Q

Q Clock

T Q

Q 0 Q 1 Q 2

Clock

Q 0

Q 1

Q 2

Count 0 7 6 5 4 3 2 1 0

Timing diagram

A three-bit down-counter

20T3 COMP3222/9222 Flip-flops L05/S42

0
0
1
1

0
1
0
1

0
1
2
3

0
0
1

0
1
0

4
5
6

1 1 7

0
0
0
0
1
1
1
1

Clock cycle

0 0 8 0

Q 2 Q1 Q0
Q 1 changes

Q 2 changes

Derivation of a synchronous up-counter
In which all output bits change at the same time
• based on T flip-flops triggered by the one clock signal

Flip-flops20T3 COMP3222/9222

T0 = 1
T1 = Q0
T2 = Q0Q1
T3 = Q0Q1Q2
…
Tn = Q0Q1…Qn-1

L05/S43

T Q

Q Clock

T Q

1
Q 0 Q 1 Q 2

Clock

Q 0

Q 1

Q 2

Count 0 1 2 3 5 9 12 14 0

Timing diagram

T Q

Q 3

4 6 8 7 10 11 13 15 1

A four-bit synchronous up-counter
Need to ensure that the clock_period ³ tcQ + delay of the AND gate chain + tsu

20T3 COMP3222/9222 Flip-flops L05/S44

T Q

Q Clock

T Q

Enable

Clear

T Q

Inclusion of an Enable and
asynchronous Clear capability

20T3 COMP3222/9222 Flip-flops L05/S45

A four-bit synchronous counter with D FFs

Clock

Enable D Q

D Q

Output
carry

D Q

Q
T

Clock

T flip-flop:
Q(t+1) = T XOR Q(t)

20T3 COMP3222/9222 Flip-flops

Can you see how you would
describe the structure in VHDL?En

Clk
Qi
Co

L05/S46

Behavioural code for a four-bit
up-counter with asynchronous clear

While not required
because of implied
memory semantics,
this statement is
included for clarity

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;

ENTITY upcount IS
PORT ( Clock, Resetn, E : IN STD_LOGIC ;

Q : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0) ) ;
END upcount;

ARCHITECTURE Behavior OF upcount IS
SIGNAL Count : STD_LOGIC_VECTOR( 3 DOWNTO 0) ;

BEGIN
PROCESS (Clock, Resetn )
BEGIN

IF Resetn = ‘0’ THEN
Count <= “0000” ; ELSIF (Clock’EVENT AND Clock = ‘1’) THEN IF E = ‘1’ THEN Count <= Count + 1 ; ELSE Count <= Count ; END IF; END IF ; END PROCESS ; Q <= Count ; END Behavior ; Needed to be able to increment Count Flip-flops Advantages of behavioural code over structural code for this design? L05/S47 Starting the count from any value • A counter with parallel-load capability Enable D Q Q Q 0 D Q Q Q 1 D Q Q Q 2 D Q Q Q 3 D 0 D 1 D 2 D 3 Load Clock Output carry 0 1 0 1 0 1 0 1 20T3 COMP3222/9222 Flip-flops L05/S48 A four-bit counter with parallel load, using INTEGER signals LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY upcount IS PORT ( R : IN INTEGER RANGE 0 TO 15 ; Clock, Resetn, L : IN STD_LOGIC ; Q : BUFFER INTEGER RANGE 0 TO 15 ) ; END upcount; ARCHITECTURE Behavior OF upcount IS BEGIN PROCESS (Clock, Resetn ) BEGIN IF Resetn = ‘0’ THEN Q <= 0 ; ELSIF (Clock’EVENT AND Clock = ‘1’) THEN` IF L = ‘1’ THEN Q <= R ; ELSE Q <= Q + 1 ; END IF; END IF ; END PROCESS ; END Behavior ; 20T3 COMP3222/9222 Flip-flops L05/S49 • A modulo-6 counter with synchronous reset Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock 1 0 0 0 Clock 0 1 2 3 4 5 0 1 Clock Count Q 0 Q 1 Q 2 Timing diagram Controlling the count range 20T3 COMP3222/9222 Flip-flops L05/S50 T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 Clock Q 0 Q 1 Q 2 Count Timing diagram 0 1 2 3 4 5 0 1 2 A modulo-6 counter with asynchronous reset Glitching is undesirable: can have unintended consequences if not designed away from the outset 20T3 COMP3222/9222 Flip-flops L05/S51 Code for a down-counter LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY downcnt IS GENERIC ( modulus : INTEGER := 8 ) ; PORT ( Clock, L, E : IN STD_LOGIC ; Q : OUT INTEGER RANGE 0 TO modulus-1 ) ; END downcnt; ARCHITECTURE Behavior OF downcnt IS SIGNAL Count : INTEGER RANGE 0 TO modulus-1 ; BEGIN PROCESS BEGIN WAIT UNTIL (Clock’EVENT AND Clock = ‘1’) ; IF L = ‘1’ THEN Count <= modulus-1 ; ELSE IF E = ‘1’ THEN Count <= Count-1 ; END IF; END IF ; END PROCESS ; Q <= Count ; END Behavior ; 20T3 COMP3222/9222 Flip-flops L05/S52 A two-digit BCD counter 20T3 COMP3222/9222 Flip-flops L05/S53 Ring counter D Q Q Clock D Q Q D Q Q Start Q 0 Q 1 Q n - 1 (a) An n -bit ring counter Clock Q 0 Start Two-bit up-counter w 0 En y 0 w 1 y 1 y 2 y 3 1 Q 1 Q 2 Q 3 2-to-4 decoder Q 1 Q 0 Clock Clear (b) A four-bit ring counter P C C 20T3 COMP3222/9222 Flip-flops L05/S54 Timing analysis of flip-flop circuits • Usually the maximum clock frequency a circuit can be operated at, Fmax, needs to be determined • Whether any hold times are violated also needs to be determined • Timing parameters of flip-flops were introduced in slides L05/S33 to L05/S38 – these include the set-up time tsu, the hold time th, and the clock-to-Q propagation delay tcQ 20T3 COMP3222/9222 Flip-flops L05/S55 Timing analysis of a simple flip-flop circuit • Consider the simple circuit shown, and let’s assume that tsu = 0.6 ns, th = 0.4 ns, and 0.8 ns <= tcQ <= 1.0 ns • Furthermore, assume the delay of a k-input gate is 1 + 0.1k ns • To calculate Tmin = 1/Fmax, we need to determine the longest timing path in the circuit (a.k.a. critical path) that starts and ends at a flip-flop • Here: Tmin = max{tcQ }+ tNOT + tsu i.e. Tmin = 1.0 + 1.1 + 0.6 = 2.7 ns and Fmax = 1/Tmin = 370 MHz any faster, and tsu would not be satisfied • Need to check hold time vio- lations by considering the shortest possible delay from any +ve clock edge to any flip-flop input • Here: min{tcQ} + tNOT = 0.8 + 1.1 = 1.9 ns > th = 0.4 ns \ no violation

20T3 COMP3222/9222 Flip-flops L05/S56

Timing analysis of a 4-bit counter
Assume the same timing

parameters as in the previous
example; critical path:

Tmin = max{tcQ(Q0)} + 3(tAND) + tXOR
+ tsu(Q3)

= 1.0 + 3(1.2) + 1.2 + 0.6
= 6.4 ns

Fmax = 1/6.4 ns = 156 MHz
(this assumes Enable is well
behaved; if not, Fmax may need
to be reduced)

Shortest path from clock to D for
each FF is min{tcQ} + tXOR = 0.8
+ 1.2 = 2.0 ns > th = 0.4 ns \
no hold violations (given Enable
is well behaved)

Flip-flops

Q: When is it best to (de)assert Enable?
L05/S57

Clock skew
• Clock skew is the spread in time (relative delay) in

clock edges arriving at the various synchronous
components of a digital circuit

• Mostly, these are caused by wire delays
• FPGAs have special clock distribution networks, which

use low-resistance (fat) wiring tracks, buffers that amplify
the clock signal, and “balanced” layouts, such as H-trees
with the root located at the centre of the chip, to
minimize clock skew

Flip-flops20T3 COMP3222/9222 L05/S58

tskew
CQ3

Effect of clock skew on Fmax

• Assume tskew = 1.5ns delay
on clock pulses arriving at
Q3

• Delay on path from Q0 to Q3 is
then given by
tcQ + 3(tAND) + tXOR + tsu – tskew =
6.4 – 1.5 = 4.9ns
since the skew provides additional
time before data is loaded into Q3

• However, critical path is now from
Q0 to Q2, i.e.
Tmin = tcQ + 2(tAND) + tXOR + tsu

= 1.0 + 2(1.2) + 1.2 + 0.6
= 5.2 ns

Fmax = 192 MHz

tCQ tAND tAND tAND tXOR tsu

CQ0-2

tCQ tAND tAND tXOR tsu

tskew

CQ0-2

CQ3

tCQ tAND tAND tAND tXOR tsu

tskew

CQ0-2

CQ3

20T3 COMP3222/9222 Flip-flops L05/S59

Negative clock skew
• A negative clock skew, i.e. clock arriving earlier at Q3

than at Q0 – Q2 would have the opposite effect of
lengthening the clock period requirement & reducing
the maximum clock frequency

20T3 COMP3222/9222 Flip-flops L05/S60

Effect of clock skew on hold times
• As positive clock skew has the effect of delaying the

loading of data into FF Q3, it has the effect of increas-
ing the hold time requirement of this FF to th + tskew for
all paths that end at Q3

• The shortest such path is from FF Q2 to Q3 and has
delay tcQ + tAND + tXOR = 0.8 + 1.2 + 1.2 = 3.2 ns > th +
tskew = 1.9 ns \ no violation

• But, when tskew ≥ 3.2 – th = 2.8 ns, then hold time
violations will exist and the circuit will not work reliably at
any frequency

• Good circuit design therefore aims to minimize, if not
eliminate, clock skew

20T3 COMP3222/9222 Flip-flops L05/S61

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