Microcomputer Systems 2. Assessment 2 – 29/11/95
Department of Electrical Engineering and Electronics
ELEC373
Digital Systems Design
Assignments 1
UAT (Universal Asynchronous Transmitter) – Assignment 1
Module ELEC373
Coursework name Assignment 1
Component weight Assignment 1 = 15%
Semester 1
HE Level 6
Lab location EEE Building PC labs 301, 304 as timetabled – Friday 2-5pm
Work Individually
Timetabled time 15 hours (3 hours per week – Friday 2pm – 5pm)
Suggested private study 10 hours including report writing
Assessment method Individual, formal word-processed reports (Block diagrams and
ASMs can be hand drawn and scanned into the report)
Submission format Online via VITAL
Submission deadline Assignment 1: Probably Friday week 7 12th November 2021
TBC
Late submission Standard university penalty applies
Resit opportunity Students Failing Assignment 1 will have Assignment 2 as the
resit opportunity.
Marking policy Marked and moderated independently
Anonymous marking Yes
Feedback Via comments on Vital submission on-line
Learning outcomes LO1: Ability to design digital systems using the ASM design method
LO2: Ability to implement digital systems using the Verilog Hardware
Description Language
Marking Criteria
Section
Marks
available
Indicative characteristics
Adequate / pass (40%) Very good / Excellent
Presentation
and structure
10%
• Contains cover page
information, table of contents,
sections with appropriate
headings.
• Comprehensible language;
punctuation, grammar and
spelling accurate.
• Equations legible, numbered
and presented correctly.
• Appropriately formatted
reference list.
• Appropriate use of technical,
mathematic and academic
terminology and conventions.
• Word processed with consistent
formatting.
• Pages numbered, figures and
tables captioned.
• All sections clearly signposted.
• Correct cross-referencing (of
figures, tables, equations) and
citations.
Introduction,
Method and
Design
50%
• Problem background
introduced clearly.
• Evidence of a Top Down Design
approach
• Conceptual Design Choices
introduced.
• Design of each module follows
a logical sequence.
• ASMs correspond to designs for
required blocks.
• Appropriate range of references
used.
• Design decisions justified with
alternatives given.
• Calculations shown in full,
justifying and explaining any
decisions.
• Correct ASM Syntax used.
• Well-structured Verilog Code
• Fully synchronous design
Results 30% • Simulation results present for
each block and well annotated.
• Results of full system in both
simulation and experimentally
presented.
• Results for each task
accompanied by a commentary.
• Screen shots of results
presented.
• Simulations demonstrate that
every pathway in each ASM is
functioning correctly.
• Tests indicate that there are no
problems caused by asynchronous
inputs.
Discussion 10% • Discussion on what worked and
what didn’t.
• Critical assessment on the
design – strength and
weaknesses
• Discussion on how the system was
fully tested.
ELEC 373 Verilog Assignment 1 (2021-2022)
Assignment Overview
These assignments have been set to get you familiar with designing digital systems and
synthesising them from a Verilog description. You should develop your design using Altera’s
Quartus II V13.0-SP1.
The first assignment is for you to undertake the full design process i.e. the conceptual design,
communicated by block diagrams, and the embodiment design communicated by ASM charts.
You should then code in Verilog and test the design on the DE2 boards in the lab. You will
use a USB->RS232 cable to connect the DE2 Board to the PC.
Assignment Outline
The DE2 Board has a 9 pin D type connector and associated level shifting circuitry to allow
the board to be connected to the RS232 port of another electronic device. Figure 1 shows the
circuit on the DE2 board which includes a MAX232 device that performs the voltage
conversion and also two LEDs which indicate if there is any activity on the transmit or receive
signals.
Figure 1 RS232 Level conversion circuit
Table 1 shows which pins of the FPGA are connected to the MAX232 device. Note that
UART_RXD is the input received signal as received on pin 3 of the 9 pin D-Type and
UART_TXD is the output transmitted signal sent to pin 2 of the 9 pin D-Type. Pin 5 carries
the GND signal between the two systems.
Table 1 FPGA Pin connections
For this first assignment you are to develop a UART transmitter to serially transmit data from
the DE2 board via the serial link to a PC running a terminal program. The PC should then
display the ASCII value of the data transmitted. For example if 0x41 was transmitted a capital
‘A’ should be displayed. The data is entered by keying in the binary data on the “inputs” and
then transmitted when the “send” key is pressed. You should also display in HEX on the seven
segment displays (indicated in Table 2) the value of the data to be transmitted. The data should
be transmitted with the baud, parity and number of bits indicated in Table 2.
Make sure that your design is fully synchronous, i.e. all the D type flipflops should be clocked
by the system clock.
You should include a top level file to connect your modules together. This top level file can be
either a “bdf” or Verilog file.
Remember you need to follow a top-down design methodology.
Report – Assignment 1
Your report should include the following.
1) Description of Architecture(s) and Controller(s) (with block diagram showing
interconnections). (Maximum 2 pages A4)
2) Description of each module to be documented by the following information
a. ASM Charts for any Algorithmic State Machines and any combinational logic
(Remember Combinational Logic can be treated as a single state ASM).
b. Commented Verilog code for each module.
c. Full simulation of each module. (With annotations indicating what the
simulation proves).
This information should be grouped together for each module i.e. there should be
a single section covering the above for each module. Don’t list all the ASMs then
all the Verilog, Document each block almost as a stand alone report.
3) Schematic of the full system.
4) Simulation of the full system. (With annotations and maximum ½ page on any
comments)
5) Explanation of experimental test results. (Max 1 page)
6) Conclusion (Maximum ½ page)
7) You should also submit your design via Canvas. Make sure all the files need to
compile simulate and test the design are included.
Please format your report in the order indicated above, i.e. fully document each module
before describing the next module.
Warning
When marking the reports I will be looking very closely for any signs of collusion, as this is
unacceptable. I need to assess your own ability not that of your friend or colleague. If I find
any evidence of collusion then the formal University rules will be followed which may result
in your suspension.
Assignment 1 Submission Deadline
Bench inspections where you will demonstrate your system 2-5pm Friday 12th November 2021
You only need to submit an Electronic copy: Friday 12th November 2021 @ 11:59pm.
You also need to submit a ZIP file of your modules by the same date and time.
J.S. Smith
15th October 2021
Table 2 – Assignment parameters
ID Student Name
Lev
el
Baud Rate Parity Data
Bits
Inputs Send
Display
201403467 Afflick, William 3 9600 Odd 7 Sw[6:0] Key0 Hex7-6
201387721 Al-Kuwari, Saad Nasser Y
S
3 19200 Odd 7 Sw[7:1] Key1 Hex6-5
201361177 Ali, Wasif 3 38400 Odd 7 Sw[8:2] Key2 Hex5-4
201414740 Barraclough, Luke 3 57600 Odd 7 Sw[9:3] Key3 Hex4-3
201357415 Chan, Alvin John 3 9600 Even 7 Sw[10:4] Key0 Hex3-2
201608805 Chapman, Kathryn Julia 3 19200 Even 7 Sw[11:5] Key1 Hex2-1
201521677 Chen, Kaien 3 38400 Even 7 Sw[12:6] Key2 Hex1-0
201520758 Chen, Yanbing 3 57600 Even 7 Sw[13:7] Key3 Hex7-6
201520796 Dong, Lizhi 3 9600 Odd 8 Sw[14:7] Key0 Hex6-5
201521819 Fan, Ye 3 19200 Odd 8 Sw[15:8] Key1 Hex5-4
201521835 Gao, Chenxi 3 38400 Odd 8 Sw[16:9] Key2 Hex4-3
201522071 Liang, Xiaotian 3 57600 Odd 8 Sw[17:10] Key3 Hex3-2
201522104 Liu, Hechen 3 9600 Even 8 Sw[7:0] Key0 Hex2-1
201522114 Liu, Mengyuan 3 19200 Even 8 Sw[8:1] Key1 Hex1-0
201431464 McNally, Jack 3 38400 Even 8 Sw[9:2] Key2 Hex7-6
201454028 Muralidharan, Sabareesh 3 57600 Even 8 Sw[10:3] Key3 Hex6-5
201522241 Qin, Xiye 3 9600 Odd 7 Sw[14:8] Key0 Hex5-4
201521147 Shen, Qifeng 3 19200 Odd 7 Sw[15:9] Key1 Hex4-3
201522275 Shu, Junyang 3 38400 Odd 7 Sw[16:10] Key2 Hex3-2
201429869 Tripathi, Roshan 3 57600 Odd 7 Sw[17:11] Key3 Hex2-1
201521301 Wu, Fan 3 9600 Even 7 Sw[10:4] Key0 Hex1-0
201448613 Xia, Lei 3 19200 Even 7 Sw[11:5] Key1 Hex7-6
201522485 Xing, Xiangjing 3 38400 Even 7 Sw[12:6] Key2 Hex6-5
201521369 Xu, Xiuyuan 3 57600 Even 7 Sw[13:7] Key3 Hex5-4
201522575 Yin, Yanyang 3 9600 Odd 8 Sw[14:7] Key0 Hex4-3
201224948 Yuan, Yifei 3 19200 Odd 8 Sw[15:8] Key1 Hex3-2
201522627 Zhang, Hailong 3 9600 Odd 8 Sw[17:10] Key2 Hex1-0
201521502 Zhang, Yechengnuo 3 19200 Odd 8 Sw[7:0] Key3 Hex7-6